Provided herein include various examples of an apparatus, a sensor system and examples of a method for manufacturing aspects of an apparatus, a sensor system. The method may include forming bumps on a surface of one or more electrical contacts, where the one or more electrical contacts are accessible on an upper surface of a die, where the die is oriented on a substrate, and where the electrical contacts comprise bonding pads. The method may also include coupling one or more additional electrical contacts to the one or more electrical contacts, where the coupling comprises wire-bonding each additional electrical contact of the additional electrical contacts to one of the one or more electrical contacts accessible on the upper surface of the die, via a portion of the bumps on the surface of the one or more electrical contacts, thereby forming wire-bonded connections.

A display device includes a display panel including a display area and a pad area. The display panel includes a base substrate, a pixel, a pad group, an alignment mark, and a protective layer. The pad group includes a plurality of pads arranged in a first direction. The alignment mark is spaced apart from the pad group in the first direction. The protective layer covers the pads and the alignment mark and a plurality of openings respectively exposing upper surfaces of the pads is defined in the protective layer. Each of the pads includes at least one pad pattern, and the alignment mark is disposed in a same layer as a pad pattern spaced farthest from the base substrate among the at least one pad pattern.

The invention provides improved techniques for bonding devices using copper-to-copper or other types of bonds. A substrate is cleaned to remove surface oxides and contaminants and then rinsed. The rinsed substrate is provided to coating unit where a protective coating is applied to the substrate. The protective coating may be applied by immersing the substrate in a bath or via chemical vapor deposition. In an aspect, the protective coating may be copper selective so that the protective coating is only applied to copper features of the substrate. The protective coating minimizes formation of oxides and other bond weakening forces that may form during bonding processes, such as bonding a copper wire to a copper bond pad of the substrate. In an aspect, an annealing process is used to cure the protective coating and remove small imperfections and other abnormalities in the protective coating prior to the bonding process.

A method of forming a semiconductor package includes forming, on a first semiconductor chip, a plurality of inner connection terminals and a preliminary underfill covering the plurality of inner connection terminals, stacking the first semiconductor chip on a lower structure such that the preliminary underfill is bonded between the first semiconductor chip and the lower structure, and curing the preliminary underfill using a laser bonding process, thereby forming a first underfill, and reflowing the plurality of inner connection terminals during a formation of the first underfill through the curing of the preliminary underfill.

Bonded die structures and methods of fabricating bonded die structures with improved stress distribution. A bonded die structure may include a second die bonded to a first die. The sizes, shapes and/or relative position of the first die with respect to the second die may be configured to minimize stress concentrations in the bonded die structure. In some embodiments, a length dimension of a corner region of the second die may be less than a length dimension of the adjacent corner region of the first die, which may aid in redistributing stress away from the corner of the first die. An offset distance between the corner of the second die and the corner of the first die may also be controlled to minimize stress applied to the corner of the first die along a vertical direction. Accordingly, crack formation may be reduced, and device performance and yields may be improved.

A connection panel unit and a display device including the same are disclosed. The connection panel unit includes a connection panel having a chip coupling region and a link region, a pad coupled to the chip coupling region, and a display driver chip coupled to the pad. The chip coupling region includes an input region and an output region spaced apart from each other. The pads include input pads coupled to the input region and output pads coupled to the output region. The ratio of pressure applied to the output pads to the pressure applied to the input pads may be between 0.9 and 1.1. The present disclosure can form an improved contact between a display driver chip and a connection panel.

A package substrate includes at least one insulating layer, upper circuit wirings having a plurality of pad patterns that extend on the at least one insulating layer, and a plurality of plating patterns respectively on the plurality of pad patterns. Each of the pad patterns has a geometric characteristic of surface waviness. Each of the plating patterns covers a surface of each of the pad patterns and has a geometric characteristic of predetermined surface roughness.

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors, the second level overlaying the first level; and at least four electronic circuit units (ECUs), where each of the ECUs include a first circuit, the first circuit including a portion of the first transistors, where each of the ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.