A temperature-sensor assembly comprising at least one temperature sensor and at least one supply line, wherein the temperature sensor has at least one electrically insulating substrate with an upper side and an underside, wherein a temperature-sensor structure with at least one sensor-contact surface is formed at least on parts of the upper side, wherein the supply line has at least one supply-line contact surface, wherein the supply-line contact surface is connected to the sensor-contact surface at least in part by means of a first sinter layer.

A method of electroplating a metal into features, having substantially different depths, of a partially fabricated electronic device on a substrate is provided. The method includes adsorbing accelerator into the bottom of recessed features; partially filling the features by a bottom up fill mechanism in an electroplating solution; diffusing leveler into shallow features to decrease the plating rate in shallow features as compared to deep features; and electroplating more metal into the features such that the height of metal in deep features is similar to the height of metal in shallow features.

Provided is a technique for enhancing the accuracy of deterioration diagnosis in a semiconductor device. The semiconductor device relating to the technique disclosed in the present specification is provided with a case, a semiconductor chip inside the case, a metal wire bonded to an upper surface of the semiconductor chip, at least one test piece inside the case, and a pair of terminals provided outside the case and connected to the test piece. The test piece is separated from the metal wire inside the case.

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a polymer layer over the metal pad. The method for forming a semiconductor structure further includes forming a seed layer over the metal pad and extending over the polymer layer and forming a conductive pillar over the seed layer. The method for forming a semiconductor structure further includes wet etching the seed layer using an etchant comprising H2O2. In addition, the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall.

A bonded structure is disclosed. The bonded structure can include an interconnect structure. The bonded structure can also include a first die directly bonded to the interconnect structure. The bonded structure can also include a second die mounted to the interconnect structure. The second die is spaced apart from the first die laterally along an upper surface of the interconnect structure. The second die is electrically connected with the first die at least partially through the interconnect structure. The bonded structure can further include a dielectric layer that is disposed over the upper surface of the interconnect structure between the first die and the second die.

An image sensor includes a stack structure including an active pixel region of pixels, and a pad region. The stack structure further includes a first substrate including a photoelectric conversion region and a floating diffusion region, a first semiconductor substrate, a first front structure arranged on a first surface of the first semiconductor substrate, a second substrate attached to the first front structure and including pixel gates, a second semiconductor substrate, and a second front structure, a third substrate attached to the second substrate and including a logic transistor for driving the pixels, and a pad arranged in the pad region. A side surface and a bottom surface of the pad are surrounded by the second front structure, and at least a portion of a top surface of the pad is exposed through a pad opening penetrating the first substrate and extending into the second substrate.

A semiconductor device includes a substrate having a first main surface and a second main surface opposite to the first main surface, and a first conductive layer including a first metal layer and a second metal layer, the first metal layer covering the second main surface, the second metal layer covering the first metal layer and including dendrites, wherein a via hole extending through the substrate and having an inner wall surface is formed in the substrate, and wherein the first metal layer, which is covered with the second metal layer, covers the inner wall surface.

A method of forming a bonding contact, a bonding structure and a semiconductor device are disclosed. The method includes forming a bonding layer. The bonding layer comprises a central region and a peripheral region. A second conductive material layer is deposited onto the surface of the bonding area, forming a capping layer. The second conductive material layer is a different conductive material from a first conductive material layer. A portion of the capping layer in the central region is removed to expose the first conductive material layer, thereby forming the bonding contact having the remaining portion of the capping layer.

An electronic device includes: a first substrate; an element layer disposed on the first substrate and including an active area and a peripheral area surrounding the active area; a first bonding pad disposed on the peripheral area of the element layer; a second substrate disposed opposite to the first substrate; a second bonding pad disposed on the second substrate and including a first part and a second part surrounding the first part; and a bonding material disposed between the first part of the second bonding pad and the first bonding pad and between the second part of the second bonding pad and the first bonding pad.

Examples of the present application provide a semiconductor structure and a fabrication method thereof, relate to the field of semiconductor chip technologies, and aim to stack more device layers in a semiconductor structure and in turn increase the number of the device layers packaged in the semiconductor structure. The semiconductor structure provided by an example of the present application includes a plurality of stack layers that are stacked and a first bonding structure, wherein two adjacent stack layers are connected together through the first bonding structure; the stack layer includes a plurality of device layers that are stacked and a second bonding structure with two adjacent device layers connected through the second bonding structure. After connecting device layers together through the second bonding structure, the thickness of the device layers can be reduced.