A resin enclosure includes: an inner wall portion from a wall surface defining the space to a side surface of the lead terminal close to the space; and a covering portion that covers at least a part of a top surface of a first portion of the lead terminal.

An electronic device includes: a first substrate; an element layer disposed on the first substrate and including an active area and a peripheral area surrounding the active area; a first bonding pad disposed on the peripheral area of the element layer; a second substrate disposed opposite to the first substrate; a second bonding pad disposed on the second substrate and including a first part and a second part surrounding the first part; and a bonding material disposed between the first part of the second bonding pad and the first bonding pad and between the second part of the second bonding pad and the first bonding pad.

A semiconductor device includes a heat sink, a base material including an insulating layer and mounted on the heat sink on one side in a first direction, a first conductive layer bonded to the base material and located on a side opposite the heat sink with respect to the base material, a first semiconductor element bonded to the first conductive layer, a first power terminal electrically connected to the first conductive layer and the first semiconductor element, and a sealing resin covering the first conductive layer and the first semiconductor element. The first power terminal is exposed from the sealing resin. The first power terminal is surrounded by a peripheral edge of the sealing resin as viewed in the first direction.

A semiconductor device according to one aspect includes a pad portion, an insulating layer that supports the pad portion, a first wiring layer that is formed in a layer below the pad portion and extends in a first direction below the pad portion, and a conductive member that is joined to a front surface of the pad portion and extends in a direction forming an angle of 30 to 30 with respect to the first direction. A semiconductor device according to another aspect includes a pad portion, an insulating layer that supports the pad portion, a first wiring layer that is formed in a layer below the pad portion and extends in a first direction below the pad portion, and a conductive member that is joined to a front surface of the pad portion and has a joint portion that is long in one direction in plan view and an angle of a long direction of the joint portion with respect to the first direction is 30 to 30.

An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

A semiconductor device includes a first die pad having a main surface, a second die pad having a second main surface, a first switching element connected to the first main surface, a second switching element connected to the second main surface, a first connecting member connecting the first main surface electrode of the first switching element to the second die pad, an encapsulation resin encapsulating the first switching element, the second switching element, the first die pad, the second die pad, and the first connecting member, and leads projecting out of one of the resin side surfaces of the encapsulation resin.

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

A semiconductor device has a joint part in which a first conducting part and a second conducting part are joined by a joint material. The first conducting part has a high wettability region and a low wettability region in a surface opposite to the second conducting part. The low wettability region is adjacent to the high wettability region to define an outer periphery of the high wettability region and has wettability lower than the high wettability region to the joint material. The high wettability region has an overlap region overlapping a formation region of the joint part in the second conducting part in a planar view, and a non-overlap region connected to the overlap region and not overlapping the formation region of the joint part in the second conducting part. The non-overlap region includes a holding region capable of holding the joint material that is surplus for the joint part.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as an element forming surface, a second main surface at a side opposite to the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, and a plurality of modified lines formed one layer each at the respective side surfaces of the SiC semiconductor layer and each extending in a band shape along a tangential direction to the first main surface of the SiC semiconductor layer and modified to be of a property differing from the SiC monocrystal.

A method of forming a semiconductor structure is provided. Two wafers are first bonded by oxide bonding. Next, the thickness of a first wafer is reduced using an ion implantation and separation approach, and a second wafer is thinned by using a removal process. First devices are formed on the first wafer, and a carrier is then attached over the first wafer, and an alignment process is performed from the bottom of the second wafer to align active regions of the second wafer for placement of the second devices with active regions of the first wafer for placement of the first devices. The second devices are then formed in the active regions of the second wafer. Furthermore, a via structure is formed through the first wafer, the second wafer and the insulation layer therebetween to connect the first and second devices on the two sides of the insulation layer.