A package structure is provided. The package structure includes a leadframe, an electronic component, an encapsulant, and a first reflowable material. The leadframe includes a first lead. The electronic component is disposed over and electrically connected to an upper surface of the leadframe. The encapsulant encapsulates the leadframe and defines a first opening exposing a first portion of a lower surface of the first lead. The first reflowable material is disposed in the first opening. The first opening is defined by curved surfaces of the encapsulant formed by etching the leadframe and has a cross-sectional profile tapering away from the first lead.

To manufacture a semiconductor device, a first heat treatment for curing a first adhesive material of a conductive paste type is performed, after a semiconductor chip is mounted on a die pad of a lead frame via the first adhesive material. After that, a metal plate is disposed on a pad of the semiconductor chip such that the metal plate faces the pad of the semiconductor chip via a second adhesive material of a conductive paste type, and a second heat treatment is performed for curing each of the first adhesive material and the second adhesive material. A time of the first heat treatment is less than a time of the second heat treatment. After the first adhesive material is cured by the first heat treatment, the first adhesive material is further cured by the second heat treatment.

Implementations of a method of providing wettable flanks on leads of a semiconductor package may include applying mold compound around a plurality of leads included in a leadframe; electroplating exposed portions of the plurality of leads; cutting at least one lead of the plurality of leads to expose a flank of the least one lead; applying an electrically conductive layer over the plurality of leads; electroplating the flank of the at least one lead to render the flank wettable; removing the electrically conductive layer from the plurality of leads; and singulating to form a semiconductor package.

A power semiconductor package includes a first substrate assembly with a power semiconductor die defining a high-side power switch, a second substrate assembly arranged parallel to the first substrate assembly which has a power semiconductor die defining a low-side power switch, and a power terminal assembly. The power terminal assembly includes a power terminal substrate arranged between the first and the second substrate assembly, a high-side drain power terminal electrically connected to an electrical drain circuit of the high-side power switch, a low-side source power terminal electrically connected to an electrical source circuit of the low-side power switch, and a mid-point power terminal electrically connected to an electrical source circuit of the high-side power switch and to an electrical drain circuit of the low-side power switch. The high-side drain power terminal, the low-side source power terminal, and the mid-point power terminal are each arranged on the power terminal substrate.

A semiconductor package comprises a lead frame, an FET, a copper layer, a source metal clip, and a molding encapsulation. The FET comprises a gate bus line, a gate electrode, and a source electrode on a top surface of the FET and a drain electrode on a bottom surface of the FET. A method comprises the steps of providing a wafer; attaching a seed layer; applying a photoresist layer; forming openings; electro plating of copper; removing the photoresist layer; removing the seed layer; applying a grinding process; applying a dicing process; attaching a lead frame; mounting source metal clips; forming a molding encapsulation; and applying a singulation process.

The disclosure is directed to wide band-gap semiconductor devices, such as power devices based on silicon carbide or gallium nitride materials. A power device die is attached to a carrier substrate or a base using sintered silver as a die attachment material or layer. The carrier substrate is, in some embodiments, copper plated with silver. The sintered silver die attachment layer is formed by sintering silver nanoparticle paste under a very low temperature, for example, lower than 200 C. and in some embodiments at about 150 C., and with no external pressures applied in the sintering process. The silver nanoparticle is synthesized through a chemical reduction process in an organic solvent. After the reduction process has completed, the organic solvent is removed through evaporation with a flux of inert gas being injected into the solution.

A semiconductor device includes: a semiconductor element; an island lead on which the semiconductor element is mounted; a terminal lead electrically connected to the semiconductor element; a wire connected to the semiconductor element and the terminal lead; and a sealing resin covering the semiconductor element, the island lead, the terminal lead, and the wire. The terminal lead includes a base member having an obverse surface facing in a thickness direction of the terminal lead, and a metal layer located between the obverse surface and the wire. The base member has a greater bonding strength with respect to the sealing resin than the metal layer. The obverse surface includes an opposing side facing the island lead. The obverse surface includes a first portion that includes at least a portion of the opposing side and that is exposed from the metal layer.

In examples, a semiconductor package includes a semiconductor die having a device side in which circuitry is formed and a non-device side opposite the device side. The package includes a die attach film contacting the non-device side of the semiconductor die; a first conductive terminal contacting the die attach film, the semiconductor die cantilevered by the first conductive terminal; a second conductive terminal separated from the die attach film, the first and second conductive terminals configured to operate in different voltage domains; bond wires coupling the device side of the semiconductor die to the first and second conductive terminals; and a mold compound contacting the semiconductor die, the die attach film, the first and second conductive terminals, and the bond wires, the mold compound present in between the die attach film and the second conductive terminal, each of the first and second conductive terminals exposed from at least one lateral surface of the mold compound.