A semiconductor package substrate includes a base substrate including a conductive material, a die pad portion, and a lead portion, a metal catalyst layer disposed on the base substrate, and a graphene layer disposed on the metal catalyst layer, wherein the semiconductor package substrate has a Vickers hardness of 135 to 150.

A method of forming a semiconductor device includes the following steps. A substrate is provided. A die is placed on the substrate, wherein an empty through hole penetrates through the die. A cavity is formed to penetrate through the substrate, to communicate with the empty through hole of the die. A liner is formed on surfaces of the empty through hole of the die and the cavity of the substrate.

A lead frame includes a base island; a plurality of leads located around the base island, the adjacent leads having between them a gap, each of the leads comprising an inner lead close to the base island and an outer lead far away from the base island, the inner lead and the outer lead being connected by a connection part; a UV tape covering at least one of a back surface or a front surface of the connection part of each of the leads and filling the gaps between the connection parts of the adjacent leads, the UV tape being configured to prevent molding layer material from overflowing in the direction of the outer leads through the gaps between the adjacent leads during subsequent formation of a molding layer covering the base island and the inner leads, and the UV tape being peeled off after irradiation by a UV light after forming the molding layer.

A method for manufacturing a singulated semiconductor product from a package is provided, and includes the steps of a) providing the bottom frame with the clip matrix with a semiconductor component and placing them in a mold cavity, b) closing the mold, c) moving retractable pins through openings in the mold, so that the tips of the pins come into contact with the tie bars or the clip tie-bars of the clip matrix, d) performing the molding operation using the encapsulating material, e) retracting the pins away from the package, f) opening the mold, g) removing the package from the mold, and h) singulating the package into a separate product by sawing along and trimming the microleads. With the above steps at least one encapsulated and singulated semiconductor product is formed, that has notches formed on the sides thereof, that expose either tie bars or clip tie-bars.

A chip package structure includes a die pad, input/output pads, a chip, first bonding wires, a molding compound, a solder resist layer, first solder balls and second solder balls. The input/output pads are configured around the die pad. The chip is configured on the die pad. The first bonding wires are electrically connected to the chip and the input/output pads. The molding compound covers the chip, the die pad, the input/output pads and the first bonding wires, and exposes a first lower surface of the die pad and a second lower surface of each input/output pad. The solder resist layer is configured on the first lower surface of the die pad and has multiple openings exposing a portion of the die pad. The first solder balls are respectively configured in the openings of the solder resist layer, and the second solder balls are respectively configured on the input/output pads.

An insulated metal substrate (1) for a power semiconductor device is specified, comprising a metal base (2), a dielectric layer (3) arranged on the metal base (2), an electrically conductive layer (4) arranged on the dielectric layer (3), and a reinforcement structure (5), wherein the reinforcement structure (5) is arranged in a peripheral region of the insulated metal substrate (1) at least partially surrounding a central region of the insulated metal substrate (1). Furthermore, a method for producing an insulated metal substrate is specified.