The present disclosure provides a packaging device and a method to form the packaging device. The packaging device includes a package base, a die structure disposed over the package base, and a package lid over the die structure. The package lid is thermally coupled with the die structure and the package base.

Systems and methods are disclosed herein to enable top-side and/or bottom-side cooling for double-sided molded (DSM) packages, thereby providing an enhanced thermal pathway to the ambient environment for densely packed DSM packages.

Methods for die attachment of multichip and single components may involve printing a sintering paste on a substrate or on the back side of a die. Printing may involve stencil printing, screen printing, or a dispensing process. Paste may be printed on the back side of an entire wafer prior to dicing, or on the back side of an individual die. Sintering films may also be fabricated and transferred to a wafer, die or substrate. A post-sintering step may increase throughput.

An electronic device includes: a first electronic component which has a Ni-based electrode; and a second electronic component which is joined to the Ni-based electrode via Sn-based solder. A (Cu, Ni, Pd).sub.6Sn.sub.5 compound layer exists at a joint interface between the Ni-based electrode and the Sn-based solder, and content of Pd existing as a (Pd, Ni)Sn.sub.4 compound in a parent phase of the Sn-based solder after joining is less than content of Pd existing as the (Cu, Ni, Pd).sub.6Sn.sub.5 compound layer or is zero.

A package substrate based on a molding process may include an encapsulation layer, a support frame located in the encapsulation layer, a base, a device located on an upper surface of the base, a copper boss located on a lower surface of the base, a conductive copper pillar layer penetrating the encapsulation layer in the height direction, and a first circuit layer and a second circuit layer over and under the encapsulation layer. The second circuit layer includes a second conductive circuit and a heat dissipation circuit, the first circuit layer and the second conductive circuit are connected conductively through the conductive copper pillar layer, the heat dissipation circuit is connected to one side of the device through the copper boss and the base, and the first circuit layer is connected to the other side of the device.

A semiconductor die assembly is introduced in this disclosure. The semiconductor die assembly includes one or more semiconductor dies, a dielectric layer disposed under a bottom surface of the one or more semiconductor dies, and metal fragments or a metal layer disposed under the dielectric layer, wherein metal-OH bonds or metal-OSiOH bonds are disposed on a bottom surface of the dielectric layer. Alternatively, the semiconductor die assembly includes one or more semiconductor dies, a metal layer disposed under a bottom surface of the one or more semiconductor dies, and a metal oxidation layer disposed under the dielectric layer, wherein the metal oxidation layer comprises metal-OH bonds or metal-OSiOH bonds.

A chip package structure includes an assembly containing an interposer and semiconductor dies; a packaging substrate attached to the assembly through solder material portions; and a lid structure attached to the packaging substrate. The lid structure includes: a first plate portion having a first thickness and located in an interposer-projection region having an areal overlap with the interposer in a plan view; a second plate portion having a second thickness that is less than the first thickness, laterally surrounding, and adjoined to, the first plate portion, and located outside the interposer-projection region; and a plurality of foot portions adjoined to the second plate portion, laterally spaced from the first plate portion, and attached to a respective top surface segment of the packaging substrate through a respective adhesive portion.

A bonded substrate structure includes a first substrate; a second substrate; and a bonding region bonding the first substrate to the second substrate. The bonding region includes an aluminum oxide bonding layer directly contacting an aluminum nitride layer, and a bonding interface between the aluminum oxide bonding layer and a bonding surface of the first substrate or the second substrate.

An IC structure includes a memory stack including semiconductor dies horizontally separate with each other, wherein each semiconductor die has a top surface, a bottom surface, four sidewalls, and a plurality of edge pads arranged along a sidewall. The IC structure further includes a memory controller under the first memory stack and electrically connected to the edge pads of each semiconductor die, a processor circuit disposed over and electrically connected to the memory controller, and a packaging substrate under and electrically connected to the memory controller. A die area of the memory controller is larger than the sum of a horizontal cross-section area of the memory stack and a die area of the processor circuit. There is no interposer between the packaging substrate and the memory controller, and there is no TSV in each semiconductor die.

A semiconductor device includes: an insulated circuit substrate including a base plate, a resin layer on the base plate, and a circuit pattern on the resin layer; a semiconductor chip that is rectangular and is bonded to the circuit pattern such that a side edge of the semiconductor chip is spaced inwardly from an outer peripheral edge of the circuit pattern by a predetermined distance; a case on the resin layer and surrounds the circuit pattern and the semiconductor chip; and a sealing material that covers the insulated circuit substrate and semiconductor chip and is surrounded by the case. The predetermined distance and thickness of the circuit pattern are greater than or equal to 0.1 of a length of one side of the semiconductor chip. A peripheral region of the case and a peripheral region of the resin layer are connected to each other via an adhesive layer.