A low warpage chip includes a chip body, a plurality of signal contacts, and an anti-warpage layer. The chip body has a back surface and an active surface opposite to each other and has a circuit layer inside. The plurality of signal contacts are configured on the active surface and are electrically connected to the circuit layer. The anti-warpage layer covers at least a part of the back surface. A thermal expansion coefficient of the anti-warpage layer is greater than a thermal expansion coefficient of the chip body. When the low warpage chip undergoes a thermal processing procedure, the anti-warpage layer mitigates the warpage of the chip body to maintain the chip body in a relatively flat state.

Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

A semiconductor package includes a semiconductor chip having Hall elements built therein, and external terminals arranged on one surface side of the semiconductor chip. A first Hall element and a second Hall element are arranged to be point-symmetrical with respect to a center point of the semiconductor package in a plan view. The first Hall element is at least partially covered by a first external terminal among first external terminals in a plan view, and the second Hall element is at least partially covered by a second external terminal among second external terminals in a plan view. A first region covered by the first external terminal of the first Hall element in a plan view and a second region covered by the second external terminal of the second Hall element in a plan view are point-symmetrical with respect to the center point of the semiconductor package in a plan view.

A package comprising a first substrate, a first integrated device coupled to the first substrate, a second substrate coupled to the first substrate through a first plurality of solder interconnects such that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate includes a first surface and a second surface, an electrical device coupled to a second surface of the second substrate such that the electrical device is located between the first substrate and the second substrate, and an encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer encapsulates the first integrated device and the electrical device.

A semiconductor package includes a first substrate including upper pads, at least one chip structure including connection pads, and first bump structures electrically connecting the connection pads and the upper pads. The connection pads include a first group of connection pads arranged at a first interval, and a second group of connection pads arranged at a second interval, smaller than the first interval. Each of the first group of the first bump structures includes a first pillar contacting one of the first group of the connection pads, and a first solder connecting the first pillar and one of the upper pads. Each of the second group of the first bump structures includes a second pillar contacting one of the second group of the connection pads, a second solder contacting one of the upper pads, and a third pillar connecting the second pillar and the second solder.

Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first substrate having first pads on a first surface of the first substrate, a second substrate on the first substrate and having a plurality of second pads on a second surface of the second substrate, and connection terminals between the first substrate and the second substrate and correspondingly coupling the first pad to the second pads. Each of the connection terminals has a first major axis and a first minor axis that are parallel to the first surface of the first substrate and are orthogonal to each other. When viewed in a plan view, the first minor axis of each of the connection terminals is directed toward a center of the first substrate.

A semiconductor package includes a film substrate that includes a chip region, a first edge region, and a second edge region. The semiconductor package includes a semiconductor chip on the chip region, where the semiconductor chip includes first conductive bumps adjacent to the first edge region and second conductive bumps adjacent to the second edge region. The semiconductor package includes first pads and second pads on the first edge region, and first lines that electrically connect ones of the first pads to ones of the first conductive bumps. The second pads are dummy pads. A first set of the second pads and a second set of the second pads are spaced apart from each other in the second direction with the first pads therebetween. The first set of second pads includes ten or more consecutive second pads with no first pads therebetween.

A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an additional bonding feature, which is non-elongated.

An electronic device realizes an antenna-in-package (AiP). The device includes a first die having a first metal layer that defines an antenna patch, a second metal layer that defines a parasitic patch above and vertically aligned with the antenna patch, and an amplifier having an output terminal electrically coupled to the antenna patch. The device further includes a second die having a metal layer that defines a reflecting patch and an interconnect that joins the first die with the second die in a vertical stack with the first die above the second die such that the antenna patch is spaced apart from, parallel to, and vertically aligned with the reflecting patch.

A chip-stacked device includes a first chip including a first substrate including a first face, a first conductive film provided in an island form over the first face and electrically connected to a signal line, and a second conductive film provided apart from the first conductive film over the first face and connected to the ground line; a second chip; a first bonding portion covering the first conductive film; and a second bonding portion apart from the first conductive film and the first bonding portion, the second bonding portion located over the second conductive film. The first chip and the second chip are bonded to each other via the first bonding portion and the second bonding portion.