A semiconductor device capable of suppressing a bonding defect between a bump of a semiconductor chip and a land of a wiring substrate is provided. The semiconductor device includes the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a wiring layer, a protective film, a first bump and a second bump. The wiring layer is formed on the semiconductor substrate and has a first bonding pad and a second bonding pad. The first bonding pad has a first upper surface. The second bonding pad has a second upper surface. The protective film is formed on the wiring layer so as to cover the first bonding pad and the second bonding pad. The protective film has a first opening portion overlapping the first bonding pad and penetrating through the protective film, and a second opening portion overlapping the second bonding pad and penetrating through the protective film.

A chip-size-package type semiconductor device includes a semiconductor layer, pads, and metal redistributions that are located above a top surface of the semiconductor layer and each of which is connected to one or more pads. The metal redistributions include first metal redistributions each of which includes a first portion and a second portion contained within the first portion in a plan view, the second portion being located above the first portion and having an area smaller than an area of the first portion in the plan view. Each of the first metal redistributions includes one or more line-shaped bends in a boundary portion between the first portion and the second portion on a surface of the first metal redistribution, the one or more line-shaped bends each having an interior angle of at least 180 degrees in a cross section of the first metal redistribution.

Microelectronic die package structures formed according to some embodiments may include a substrate having one or more solder structures. A first set of solder structures is located in a peripheral region of the substrate and a second set of solder structures is located in a central region of the substrate. A height of individual ones of the second set of solder structures is greater than a height of individual ones of the first set of solder structures. A die having a first side and a second side includes one or more conductive die pads on the first side, where individual ones of the conductive die pads are on individual ones of the first set solder structures and on individual ones of the second set solder structures. A die backside layer is on the second side of the die.

Embodiments of the subject disclosure are directed to, for example, a circuit or device that includes a package corresponding to a first waveguide, a die corresponding to a second waveguide, and an array of bump balls disposed between the package and the die. Various embodiments may include a circuit or device that includes a plurality of ground planes, a plurality of ground bump balls, and a plurality of package ground planes, where the plurality of ground planes, the plurality of ground bump balls, and the plurality of package ground planes form a Faraday cage. Other embodiments are disclosed.

A semiconductor package includes a first semiconductor chip having a dummy region, a connection region, and a lower conductive structure disposed below the connection region; bump structures including a first bump structure on the lower conductive structure and a second bump structure below the dummy region; an interposer having the first semiconductor chip mounted thereon and upper conductive structures disposed in an upper portion thereof; connection bumps disposed on upper portions of the upper conductive structures: including a first connection bump in contact with the first bump structure and a second connection bump in contact with the second bump structure; and at least one second semiconductor chip mounted on the interposer adjacent to the first semiconductor chip. The second bump structure includes a portion with a tapering width toward the second connection bump, an end of the second bump structure is inserted into the second connection bump.

A semiconductor package includes a semiconductor chip including a semiconductor substrate having an active layer, ground chip pads on the semiconductor substrate, and signal chip pads on the semiconductor substrate and a package substrate supporting the semiconductor chip, the package substrate including a substrate insulating layer, a plurality of signal line patterns extending in the substrate insulating layer and electrically connected to the signal chip pads, and a plurality of ground line patterns extending in the substrate insulating layer at a same level as a level of the plurality of signal line patterns and electrically connected to the ground chip pads. At least one of the plurality of ground line patterns extends between the plurality of signal line patterns.

A semiconductor structure and semiconductor device are provided. The semiconductor structure includes a plurality of layers of memory modules stacked on an upper surface of the logic chip in a first direction which is perpendicular to the upper surface of the logic chip. Each storage module includes a plurality of memory chips stacked in a second direction which is parallel to the upper surface. Each memory chip in a top layer includes one second wireless communication part; and each memory chip in a non-top layer includes two second wireless communication parts arranged in the first direction and a wired communication part connected between the two second wireless communication parts. Two adjacent second wireless communication parts located on different memory chips in the first direction communicate with each other wirelessly; and each first wireless communication part communicates wirelessly with a closest second wireless communication part in a bottom memory chip.

A semiconductor structure, a method for preparing the semiconductor structure and a memory are provided. The method includes: providing a wafer in which multiple conductive pillars are formed; inverting the wafer and performing etching on a back plane of the wafer to expose each conductive pillar from the back plane of the wafer, and lengths of the multiple conductive pillars exposed to the back plane are different; depositing an insulation layer on the back plane of the wafer and the conductive pillars, and depositing a filling layer on the insulation layer, the filling layer completely covering back ends of the multiple conductive pillars; and performing polishing on the filling layer and back ends of a part of the conductive pillars, until a back end of each conductive pillar is exposed and the back ends of the multiple conductive pillars are flush with a back plane of the filling layer.

A package comprising a substrate comprising at least one dielectric layer and a plurality of interconnects; a first integrated device coupled to the substrate through a first plurality of solder interconnects, wherein the first plurality of solder interconnects includes a first plurality of inner solder interconnects and a first plurality of perimeter solder interconnects; and a second integrated device coupled to the substrate through a second plurality of solder interconnects. The first integrated device is configured to be electrically coupled to the second integrated device through an electrical path. The electrical path comprises an inner solder interconnect from the first plurality of inner solder interconnects, at least one interconnect from the plurality of interconnects, and a solder interconnect from the second plurality of solder interconnects.

Semiconductor systems and methods of manufacturing the semiconductor systems are provided. The semiconductor systems may include a plurality of components, wherein dimensions and/or relationships of the components and their connection regions conform with design rules that enable the components and their interconnectors to be assembled together in various configurations.