An exemplary hearing device includes a housing and a chip package disposed within the housing. The chip package may comprise a printed circuit board, an integrated circuit configured to perform an electronic function associated with the hearing device, and a plurality of solder bumps on a bottom surface of the integrated circuit. The plurality of solder bumps may provide conductive connectivity between the integrated circuit and the printed circuit board. The plurality of solder bumps may comprise a first group of solder bumps located within a center region of the bottom surface of the integrated circuit and a second group of solder bumps located within a peripheral region of the bottom surface, the peripheral region surrounding the center region. All signals required for the integrated circuit to perform the electronic function may be provided by way of the first group of solder bumps.

A semiconductor device has a semiconductor wafer or substrate including a plurality of semiconductor die. A plurality of first bumps is formed over an active surface of the semiconductor wafer. A plurality of second bumps is formed within a saw street of the semiconductor wafer separating the plurality of semiconductor die. A top surface of the first bumps is coplanar with a top surface of the second bumps. The second bumps are formed within a first saw street of the semiconductor wafer and further within a second saw street of the semiconductor wafer different from the first saw street. The first bumps are electrically connected to the semiconductor die to provide a function for the semiconductor die. The second bumps are dummy bumps that have no electrical function for the semiconductor die. The semiconductor wafer is singulated through the saw street and second bumps.

A semiconductor package includes a semiconductor chip including a semiconductor substrate having an active layer, ground chip pads on the semiconductor substrate, and signal chip pads on the semiconductor substrate and a package substrate supporting the semiconductor chip, the package substrate including a substrate insulating layer, a plurality of signal line patterns extending in the substrate insulating layer and electrically connected to the signal chip pads, and a plurality of ground line patterns extending in the substrate insulating layer at a same level as a level of the plurality of signal line patterns and electrically connected to the ground chip pads. At least one of the plurality of ground line patterns extends between the plurality of signal line patterns.

An integrated circuit device, having a first number of terminals, and a first plurality of functional circuits including a second number of functional circuits requiring access to the terminals in the first number of terminals, where the second number is greater than the first number, includes a second plurality of functional circuits from among the first plurality of functional circuits, the second plurality of functional circuits sharing access to a shared terminal among the first number of terminals, and a respective isolation circuit between the shared terminal among the first number of terminals and each respective functional circuit in the second plurality of functional circuits, the respective isolation circuit being configured to prevent coupling of noise from one respective functional circuit in the second plurality of functional circuits to another respective functional circuit in the second plurality of functional circuits via the shared terminal.

A semiconductor package includes a package base substrate including a potential plate. An interposer is arranged on the package base substrate and comprises at least one interposer through electrode, at least one first connection bump, and at least one second connection bump. A first stacked chip unit is arranged on the interposer and comprises a first semiconductor chip and at least one second semiconductor chips arranged on the first semiconductor chip. At least one passive device unit is arranged on the package base substrate. The at least one passive device unit is spaced apart from the interposer in a horizontal direction parallel to an upper surface of the package base substrate. The at least one first connection bump is a dummy bump. The potential plate electrically connects the at least one first connection bump and a power terminal of the at least one passive device unit to each other.

An electronic device, includes: (i) a processing chiplet configured to process data and having a first side and a second side, (ii) one or more first static random-access memory (SRAM) chiplets disposed on the first side of the processing chiplet and configured to store a first portion of the data, (iii) one or more second SRAM chiplets disposed on the second side of the processing chiplet and configured to store a second portion of the data, (iv) one or more first electrical terminals disposed on the first side of the processing chiplet and configured to electrically connect between the first side of the processing chiplet and the first SRAM chiplets, and (v) one or more second electrical terminals disposed on the second side of the processing chiplet and configured to electrically connect between the second side of the processing chiplet and the second SRAM chiplets.

A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.

A semiconductor package includes a semiconductor chip having Hall elements built therein, and external terminals arranged on one surface side of the semiconductor chip. A first Hall element and a second Hall element are arranged to be point-symmetrical with respect to a center point of the semiconductor package in a plan view. The first Hall element is at least partially covered by a first external terminal among first external terminals in a plan view, and the second Hall element is at least partially covered by a second external terminal among second external terminals in a plan view. A first region covered by the first external terminal of the first Hall element in a plan view and a second region covered by the second external terminal of the second Hall element in a plan view are point-symmetrical with respect to the center point of the semiconductor package in a plan view.

A semiconductor chip including a plurality of first pads, a plurality of second pads, a plurality of first bumps, and a plurality of second bumps is provided. The first pads and the second pads are arranged along a direction of a long side of an active surface of the semiconductor chip. The first bumps are disposed on the first pads, and configured for a chip probe test. The second bumps are disposed on the second pads, and not for the chip probe test. A size of the first bump is larger than a size of the second bump.

In one example, an electronic device comprises a substrate having a first conductive structure, an electronic component coupled to the first conductive structure at a first side of the substrate, wherein the electronic component includes a first side facing the first side of the substrate and a second side opposite the first side, vertical interconnects around the electronic component, wherein the vertical interconnects are coupled to the first conductive structure at the first side of the substrate, an interposer having a second conductive structure coupled to the plurality of vertical interconnects, a thermal body coupled between the electronic component and the interposer, and an encapsulant between the substrate and the interposer, around the thermal body, around the plurality of vertical interconnects, and around the electronic component. Other examples and related methods are also disclosed herein.