Provided are a semiconductor structure and a method of forming the same. The semiconductor structure includes: a substrate, an under bump metallurgy (UBM) structure, and a solder. The UBM structure is disposed over the substrate. The UBM structure includes a first metal layer; a second metal layer disposed on the first metal layer; and a third metal layer disposed on the second metal layer. A sidewall of the first metal layer is substantially aligned with a sidewall of the second metal layer, and a sidewall of the third metal layer is laterally offset inwardly from the sidewalls of the first and second metal layers. The solder is disposed on the third metal layer.

Compact inductors are disclosed herein. In certain embodiments, a compact inductor includes a ferrite core including a ferrite body, and a first conductive pillar and a second conductive pillar that each extend from a bottom surface of the ferrite body to a top surface of the ferrite body. Additionally, the compact inductor includes a planar substrate coupled to the top surface of the ferrite body. The planar substrate includes interconnect that electrically connects the first conductive pillar to the second conductive pillar.

An inspection pattern capable of performing wafer-level automatic inspection using a cantilever-type probe card is provided. An inspection pattern according to one embodiment of the present disclosure includes: a Cu pillar pad formed on a semiconductor substrate; a Cu pillar formed on the Cu pillar pad; and an inspection pad formed on the semiconductor substrate, electrically coupled adjacent to or proximate to the Cu pillar pad, and configured to provide a region that a cantilever-type probe comes in contact with during wafer-level automatic inspection.

According to one aspect, a semiconductor package structure is provided. The semiconductor package structure includes: a plurality of first semiconductor chips arranged as being stacked along a first direction, the first semiconductor chip includes at least one first conductive structure, the first conductive structure includes a first connection structure extending along the first direction, a second connection structure extending along the first direction, and an interconnection structure between the first connection structure and the second connection structure in the first direction, and the interconnection structure is connected with both the first connection structure and the second connection structure; and a first bump connection layer between two adjacent ones of the first semiconductor chips in the first direction, the first bump connection layer includes at least one first bump structure, and the first bump structure is coupled with each of the first conductive structures in the two adjacent first semiconductor chips.

A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

An electronic device includes: a first insulating layer; a first metal bump disposed on the first insulating layer; a second insulating layer disposed on the first metal bump; a metal layer, wherein the first insulating layer is disposed between the second insulating layer and the metal layer; a second metal bump disposed between the metal layer and the first insulating layer, wherein the second metal bump electrically connects to the first metal bump; a third insulating layer disposed between the second metal bump and the first insulating layer, wherein the third insulating layer includes an opening exposing a portion of the second metal bump; and a fourth insulating layer disposed between the third insulating layer and the first insulating layer, wherein a portion of the fourth insulating layer extends and is disposed in the opening to contact the second metal bump.

A semiconductor module may include a package substrate including a first surface and an opposite second surface, a semiconductor chip on the first surface of the package substrate, a plurality of pads on the second surface of the package substrate, and a plurality of solder balls connected to the plurality of pads, respectively, where the package substrate may include a slit in or on the second surface, at least a portion of the slit is disposed between the plurality of solder balls, the slit is spaced apart from the plurality of pads, and a filling layer is in the slit.

Disclosed are semiconductor packages and their fabricating methods. A semiconductor package includes a first semiconductor die, a second semiconductor die on the first semiconductor die, an underfill layer between the first semiconductor die and the second semiconductor die, and a mold layer on a top surface of the first semiconductor die and a lateral surface of the second semiconductor die. The first semiconductor die includes a first semiconductor substrate and an edge conductive pad on a rear surface of the first semiconductor substrate. One portion of the edge conductive pad overlaps the second semiconductor die. Another portion of the edge conductive pad is covered with the mold layer.

A method of forming a semiconductor package includes forming, on a first semiconductor chip, a plurality of inner connection terminals and a preliminary underfill covering the plurality of inner connection terminals, stacking the first semiconductor chip on a lower structure such that the preliminary underfill is bonded between the first semiconductor chip and the lower structure, and curing the preliminary underfill using a laser bonding process, thereby forming a first underfill, and reflowing the plurality of inner connection terminals during a formation of the first underfill through the curing of the preliminary underfill.

Structures for a photonic chip and associated methods. The structure comprises a photonic chip including a bond pad and forming an electrical interconnection that includes a pillar positioned on the bond pad. The pillar includes a first lobed section, a second lobed section spaced from the first lobed section by a gap, and a connecting section extending across a portion of the gap to connect the first lobed section to the second lobed section.