In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

A semiconductor device includes a first die, a second die, a first redistribution layer (RDL) structure and a connector. The RDL structure is disposed between the first die and the second die and is electrically connected to the first die and the second die and includes a first polymer layer, a second polymer layer, a first conductive pattern and an adhesion promoter layer. The adhesion promoter layer is between and in direct contact with the second polymer layer and the first conductive pattern. The connector is disposed in the first polymer layer and in direct contact with the second die and the first conductive pattern.

Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method of processing a substrate includes: forming a first patterned mask on a substrate made of glass; etching exposed portions of the substrate to form a plurality of blind vias; removing the first patterned mask; forming a second patterned mask on the substrate after removing the first patterned mask; etching exposed second portions of the substrate to form a redistribution layer (RDL) pattern at an upper portion of at least one of the plurality of blind vias; depositing a seed layer in the plurality of blind vias and the RDL pattern; and filling the plurality of blind vias and the RDL pattern with a metal material to form a plurality of filled vias and a redistribution layer (RDL).

A circuit structure includes a low-density conductive structure, a high-density conductive structure and a plurality of traces. The high-density conductive structure is disposed over the low-density conductive structure, and defines an opening extending from a top surface of the high-density conductive structure to a bottom surface of the high-density conductive structure. The opening exposes a first pad of the low-density conductive structure and a second pad of the low-density conductive structure. The second pad is spaced apart from the first pad. The traces extend from the top surface of the high-density conductive structure into the opening. The traces include a first trace connecting to the first pad of the low-density conductive structure and a second trace connecting to the second pad of the low-density conductive structure.

An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure including dielectric layers and metallization patterns therein, the metallization patterns including a top metal layer including top metal structures, forming a passivation layer over the top metal structures of the first interconnect structure, forming a first opening through the passivation layer, forming a probe pad in the first opening and over the passivation layer, the probe pad being electrically connected to the first top metal structure, performing a circuit probe test on the probe pad, removing the probe pad, and forming a bond pad and a bond via in dielectric layers over the passivation layer, the bond pad and bond via being electrically coupled to a second top metal structure of the top metal structures and a third top metal structure of the top metal structures.

A package structure and method of forming the same are provided. The package structure includes a die, a through via, an encapsulant, an adhesion promoter layer, an insulating layer and a polymer layer. The through via is laterally aside the die. The encapsulant laterally encapsulates the die and the a through via. The adhesion promoter layer and an insulating layer are sandwiched between the a through via and the encapsulant. Sidewalls of the a through via are covered by the adhesion promoter layer and the insulating layer. The polymer layer is located under the through via and encapsulant. The insulating layer includes a plurality of portions.