A method for fabricating a package structure is provided. The method includes forming a metal layer over a carrier substrate. The method includes forming a dielectric layer over the metal layer. The method includes forming a plurality of first openings in the dielectric layer. The method includes forming a plurality of second openings in the dielectric layer. The first openings and the second openings expose the metal layer. The method includes forming a conductive material in the first openings and the second openings to form a plurality of conductive features. The method includes removing the metal layer and the carrier substrate. The method includes thinning the dielectric layer around the conductive features. The method also includes bonding a package component to the conductive features.

A semiconductor device has a photonic semiconductor die. The photonic semiconductor die is disposed on a carrier with a photonic circuit of the photonic semiconductor die oriented toward the carrier. An e-bar is disposed on the carrier. An encapsulant is deposited over the photonic semiconductor die and e-bar. A first surface of the encapsulant is backgrinded to expose the e-bar. A first build-up interconnect structure is formed over the first surface of the encapsulant. A second build-up interconnect structure is formed over a second surface of the encapsulant. The photonic circuit is exposed through an opening of the second build-up interconnect structure.

A packaged transistor device includes an RF signal input lead, an RF signal output lead, and a discrete transistor having a transistor structure arranged and/or formed on a substrate. The packaged transistor device also includes at least one harmonic reduction circuit arranged and/or formed on the substrate of the discrete transistor.

A semiconductor device, including: a board having an upper surface, a lower surface, and a side surface; and a sealing member having a lower surface and an opening in the lower surface thereof, the opening having an inclined side surface therein, the sealing member sealing the upper surface and the side surface of the board, leaving the entire lower surface of the board exposed from the opening, so as to form: an under-board space directly below the lower surface of the board, and a lateral space directly below the inclined side surface of the opening, and continuous with the under-board space.

A semiconductor package includes a substrate including a first surface and a second surface, and a first substrate pad on the second surface, a first semiconductor chip on the second surface and including a third surface and a fourth surface, a first hotspot within the first semiconductor chip, and a first chip pad on the fourth surface, a first dummy pad on the fourth surface, a first layer connecting the first hotspot and the first dummy pad, a first pillar on the first dummy pad, a mold film on the substrate and including a fifth surface and a sixth surface, a thermal interface material layer on the mold film, and a heat slug on the thermal interface material layer; the mold film includes a first recess recessed inwardly from the sixth surface of the mold film, and at least part of the thermal interface material layer is in the recess.

Implementations described herein relate to various semiconductor device assemblies. In some implementations, an apparatus includes a first integrated circuit die conjoined with a second integrated circuit die in a stack of integrated circuit dies, where the first integrated circuit die includes an end region that extends beyond an edge of the second integrated circuit die. The apparatus includes an interconnect structure that is conjoined with the end region and is electrically coupled to integrated circuitry of the first integrated circuit die and a casing that encapsulates at least a portion of the interconnect structure, at least a portion of the first integrated circuit die, and at least a portion of the second integrated circuit die. The apparatus includes an electrical trace that is conjoined with a surface of the casing, is disposed along a contour of the casing, and is electrically coupled to the interconnect structure.

A package and method is disclosed. In one example, the package comprises a carrier comprising a component mounting area from which a tie bar extends, the tie bar being configured for being clamped by an encapsulation tool pin during encapsulation, an electronic component mounted on the component mounting area, and an encapsulant encapsulating at least part of the electronic component and part of the carrier and having a sidewall with a sidewall recess which is vertically displaced with respect to a part of the tie bar, wherein the encapsulant vertically covers an entire horizontal surface portion of the tie bar facing the sidewall recess.

A package comprising a first substrate; an integrated device coupled to the first substrate, wherein the integrated device comprises a plurality of back side metallization interconnects; and a second substrate coupled to the first substrate through a first plurality of solder interconnects, wherein the second substrate is coupled to the plurality of back side metallization interconnects through the second plurality of solder interconnects.

In one example, an electronic device, comprises a substrate comprising a first side and a second side opposite to the first side, wherein the substrate comprises dimples on the first side of the substrate, an electronic component over the first side of the substrate, an encapsulant over the first side of the substrate and covering a lateral side of the electronic component, and a first interconnect in the encapsulant and coupled to the electronic component and the substrate. Other examples and related methods are also disclosed herein.

Implementations of a semiconductor package may include one or more leads operatively coupled with one or more semiconductor devices; and a mold compound coupled to the one or more leads and exposing a flank of the one or more leads through a surface of the mold compound that may be oriented substantially perpendicularly to a longest length of the one or more leads. An exposed surface of the flank may be recessed into the surface of the mold compound. The exposed surface of the flank may include at least one curve.