An encapsulation of laser direct structuring (LDS) material is molded onto a substrate having first and second semiconductor dice arranged thereon. Laser beam energy is applied to a surface of the encapsulation of LDS material to structure therein die vias extending through the LDS material to the first and second semiconductor dice and a die-to-die line extending at surface of the LDS material between die vias. Laser-induced forward transfer (LIFT) processing is applied to transfer electrically conductive material to the die vias and the die-to-die line extending between die vias. A layer of electrically conductive material electroless grown onto the die vias and the die-to-die line facilitates improved adhesion of the electrically conductive material transferred via LIFT processing.

A semiconductor device includes a first redistribution structure, a first semiconductor package, a second semiconductor package, an encapsulation layer, a first thermal interface material (TIM) layer, and a second TIM layer. The first semiconductor package and the second semiconductor package are respectively disposed on the first redistribution structure and laterally disposed aside with each other. The encapsulation layer encapsulates and surrounds the first semiconductor package and the second semiconductor package. The first semiconductor package and the second semiconductor package are respectively exposed from the encapsulation layer. The first TIM layer and the second TIM layer are respectively disposed on back surfaces of the first semiconductor package and the second semiconductor package. A top surface of the first TIM layer and a top surface of the second TIM layer are coplanar with a top surface of the encapsulation layer.

A semiconductor device has a substrate and a first light sensitive material formed over the substrate. A plurality of first conductive posts is formed over the substrate by patterning the first light sensitive material and filling the pattern with a conductive material. A plurality of electrical contacts is formed over the substrate and the conductive posts are formed over the electrical contacts. A first electric component is disposed over the substrate between the first conductive posts. A plurality of second conductive posts is formed over the first electrical component by patterning a second light sensitive material and filling the pattern with conductive material. A first encapsulant is deposited over the first electrical component and conductive posts. A portion of the first encapsulant is removed to expose the first conductive posts. A second electrical component is disposed over the first electrical component and covered with a second encapsulant.

An integrated circuit die includes a semiconductor substrate, an interconnect layer including bonding pads, and a passivation layer covering the interconnect layer and including openings at the bonding pads. A conductive redistribution layer including conductive lines and conductive vias is supported by the passivation layer. An insulating layer covers the conductive redistribution layer and the passivation layer. Channels formed in an upper surface of the insulating layer delimit pedestal regions in the insulating layer. A through via extends from an upper surface of each pedestal region through the pedestal region and the insulating layer to reach and make contact with a portion of the conductive redistribution layer. A metal pad is formed at the upper surface of each pedestal region in contact with its associated through via. The metal pads for leads of a quad-flat no-lead (QFN) type package.

Reliability of a semiconductor device is improved. The semiconductor device includes a clip which is electrically connected to a main-transistor source pad via a first silver paste and is connected to a lead via a second silver paste. The clip has a first part with which the first silver paste is in contact, a second part with which the second silver paste is in contact, and a third part positioned between the first part and the second part. A protruding member is formed on a surface of the main-transistor source pad, and the first part is in contact with the protruding member.

Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

Various aspects of the present disclosure generally relate to an integrated circuit device, such as a packaged integrated circuit device. In some aspects, an integrated circuit device includes a semiconductor die and a lid thermally coupled to the semiconductor die. The lid includes a two-phase thermal management device. The integrated circuit device also includes an interface layer in contact with the semiconductor die and the lid.

The present disclosure relates to a flip-chip based moisture-resistant module, which includes a substrate with a top surface, a flip-chip die, a sheet-mold film, and a barrier layer. The flip-chip die has a die body and a number of interconnects, each of which extends outward from a bottom surface of the die body and is attached to the top surface of the substrate. The sheet-mold film directly encapsulates sides of the die body, extends towards the top surface of the substrate, and directly adheres to the top surface of the substrate, such that an air-cavity with a perimeter defined by the sheet-mold film is formed between the bottom surface of the die body and the top surface of the substrate. The barrier layer is formed directly over the sheet-mold film, fully covers the sides of the die body, and extends horizontally beyond the flip-chip die.

A semiconductor package includes a laminate package substrate, first and second power transistor dies embedded within the laminate package substrate, a driver die embedded within the laminate package substrate, a plurality of I/O routings electrically connected with I/O terminals of the driver die, a switching signal pad electrically connected with a second load terminal of the first power transistor die and a first load terminal of the second power transistor die, and a shielding pad that is configured to electrically shield at least one of the I/O routings from the switching signal pad during operation of the first and second power transistor dies, wherein the shielding pad is exposed from the electrically insulating layer.

An electronic package is provided. The electronic package comprises a substrate having a first side and a second side, the substrate configured to receive one or more electronic components; a first electronic component mounted to the first side of the substrate; a first mold structure extending over at least part of the first side of the substrate; a group of through-mold connections provided on the first side of the substrate, the through-mold connections substantially formed of non-reflowable electrically conductive material; the first mold structure substantially encapsulating the group of through-mold connections; the group of through-mold connections exposed through the first mold structure. An electronic device comprising such an electronic package is also provided. A method of manufacturing such an electronic package is also provided.