An optical sensor package includes a light-emitting unit disposed on a package substrate and configured to emit first light toward a target, a light-receiving unit disposed on the package substrate and configured to receive second light obtained when the first light is reflected from the target, and a molding member formed on the package substrate to surround a top surface of an exposed portion of the package substrate, the light-emitting unit, and the light-receiving unit, the molding member including a groove formed in a thickness direction between the light-emitting unit and the light-receiving unit, wherein the groove is filled with an opaque material.

A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a first semiconductor device mounted on the redistribution structure, vertical connection conductors on the redistribution structure and apart from the first semiconductor device in a horizontal direction, a second semiconductor device mounted on the vertical connection conductors, and a heat-dissipation plate mounted on the first semiconductor device, wherein the heat-dissipation plate includes a main body and a plurality of protrusions protruding from the main body in the horizontal direction.

A semiconductor package includes: a molded body having opposite first and second sides; at least one semiconductor die encapsulated by the molded body; and a die carrier having opposite first and second sides. The semiconductor die is arranged over the first side of the die carrier. The second side of the die carrier is at least partially exposed from the second side of the molded body, forming at least one exposed portion of the die carrier. The first side of the molded body includes a first portion protruding from a second portion in a vertical direction perpendicular to the first side, forming a planar surface. The second portion extends completely along at least one edge of the first side. A center point of the first portion is in vertical alignment with a center point of the exposed portion.

An integrated sensor component includes a chip carrier and a first semiconductor chip and a second semiconductor chip, wherein either both semiconductor chips are arranged on the chip carrier or (alternatively) the second semiconductor chip is arranged on the chip carrier and the first semiconductor chip is arranged on the second semiconductor chip (chip-on-chip). The integrated sensor component further includes a first sensor element integrated in the first semiconductor chip and a second sensor element integrated in the second semiconductor chip, as well as a housing formed by a potting compound, which has an opening. Both the first sensor element and the second sensor element are located within the opening so that they can interact with the atmosphere surrounding the sensor component.

Semiconductor packages, and methods for manufacturing semiconductor packages are provided. In one aspect, a method of manufacturing a semiconductor package includes stacking a plurality of semiconductor chips including a first semiconductor chip and a second semiconductor chip, the first semiconductor ship being offset from the second semiconductor ship to expose upper connection pads; forming a multilayered photoresist film to cover the plurality of semiconductor chips; forming a plurality of openings by exposing and developing the multilayered photoresist film; forming a plurality of conductive posts by filling the plurality of openings with a conductive material; removing the multilayered photoresist film; forming a molding encapsulant to surround the plurality of semiconductor chips and the plurality of conductive posts; and forming a wiring structure electrically connected to the plurality of conductive posts. The multilayered photoresist film comprises at least two layers having different chemical resistances and resolutions.

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.

A semiconductor package including a lower substrate, a lower semiconductor chip mounted on the lower substrate, a lower mold layer on the lower substrate and enclosing the lower semiconductor chip, a redistribution layer on the lower mold layer, and a vertical connection terminal around the lower semiconductor chip and connecting the lower substrate to the redistribution layer may be provided. The lower semiconductor chip may include a cognition mark at a top surface thereof. The cognition mark may include a marking pattern having an intaglio shape at the top surface of the lower semiconductor chip, and a molding pattern filling an inner space of the marking pattern. A first material constituting the molding pattern may be the same as a second material constituting the lower mold layer.

A semiconductor die is proposed, wherein the semiconductor die comprises a microelectronic section and a sensor section. The microclectronic section comprises an integrated circuit. The sensor section adjoins an edge of the semiconductor die. A sensor is also proposed, which comprises such a semiconductor die.

A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.