A semiconductor package structure includes a base having a first surface and a second surface opposite thereto, wherein the base comprises a wiring structure, a first electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, a second electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, wherein the first electronic component and the second electronic component are separated by a molding material, a first hole and a second hole formed on the second surface of the base, and a frame disposed over the first surface of the base, wherein the frame surrounds the first electronic component and the second electronic component.

A display panel and a display device are provided, wherein a terminal region of the display panel includes a first terminal region, a second terminal region, and a third terminal region. The display panel includes a plurality of first terminals and a second terminal, each of the plurality of first terminals is located in the first terminal region and close to the second terminal region, and the second terminal is located in the second terminal region and electrically connected to the first terminal by a first trace. A length direction of the first terminal extends through the second terminal region, and the first trace is located between the first terminal region and the second terminal region.

A semiconductor package, as a semiconductor package mounted on a circuit board, includes including: a body portion including a semiconductor chip, and a first surface and a second surface opposite to each other; and a structure including n insulating layers stacked on at least one of the first surface and the second surface of the body portion, wherein the semiconductor package has a predetermined target coefficient of thermal expansion (CTE), and the n insulating layers and the body portion have a thickness and a CTE satisfying a condition that an effective CTE of the semiconductor package becomes equal to the predetermined target CTE.

This document discloses techniques, apparatuses, and systems relating to a package substrate for a semiconductor device. A semiconductor device assembly is described that includes a packaged semiconductor device having one or more semiconductor dies coupled to a package-level substrate. The package-level substrate has a first surface at which first contact pads are disposed in a first configuration. The packaged semiconductor device is coupled with an additional package-level substrate that includes a second surface having second contact pads disposed in the first configuration and a third surface having third contact pads disposed in a second configuration different from the first configuration. The additional package-level substrate includes circuitry coupling the second contact pads the third contact pads to provide connectivity at the third contact pads. In doing so, an adaptively compatible semiconductor device may be assembled.

A semiconductor package includes a redistribution structure including a wiring structure and an insulating structure covering the wiring structure, the redistribution structure having a first surface and a second surface, which are opposite to each other, the insulating structure including a polymer, a semiconductor chip on the first surface, the semiconductor chip being connected to at least one first wiring pattern in the wiring structure, a passivation insulating film covering the second surface, the passivation insulating film including an inner surface contacting the insulating structure and a hole sidewall defining a hole, the passivation insulating film including an inorganic insulating material, a conductive pad passing through the passivation insulating film via the hole and contacting the second wiring pattern, the conductive pad having a pad sidewall contacting the hole sidewall, and an external connection terminal on the conductive pad.

An interposer configured for connecting offset arrays of signal pads on parallel surfaces. Contacts of the interposer have mating portions with multiple beams. One of the beams makes contact with a pad on a first of the surfaces and is deflected when the surfaces are pressed together with the interposer between them. A second of the beams is positioned so that the first beam presses into that second beam as the first beam deflects. The second beam may contact a central location on the first beam. An electrical path through the contact from a pad on the first surface to a pad on the second surface may be shorter when the first beam is pressed into the second beam than through the first beam alone. A shorter path may improve signal integrity. Moreover, the spring force of the contact may be set by the second beam.

A semiconductor device includes a first redistribution structure, a first semiconductor package, a second semiconductor package, an encapsulation layer, a first thermal interface material (TIM) layer, and a second TIM layer. The first semiconductor package and the second semiconductor package are respectively disposed on the first redistribution structure and laterally disposed aside with each other. The encapsulation layer encapsulates and surrounds the first semiconductor package and the second semiconductor package. The first semiconductor package and the second semiconductor package are respectively exposed from the encapsulation layer. The first TIM layer and the second TIM layer are respectively disposed on back surfaces of the first semiconductor package and the second semiconductor package. A top surface of the first TIM layer and a top surface of the second TIM layer are coplanar with a top surface of the encapsulation layer.

This disclosure relates to a light-emitting substrate, a preparation method thereof, and an array substrate, and relates to the technical field of display. The array substrate is polygonal and has at least one set of first and second lateral sides oppositely arranged, and has a first binding area arranged near the first lateral side and a second binding area arranged near the second lateral side. The array substrate includes a base substrate and a pad layer arranged on a main surface of the base substrate. The pad layer includes first binding pads in the first binding area, and second binding pads in the second binding area. Any one of the first binding area and the second binding area is configured to connect with a driving circuit board to drive the array substrate. The array substrate can avoid the binding pad from being damaged and thus discarding the array substrate.

An electronic package is provided, in which an electronic element is arranged on a carrier structure having a plurality of wire-bonding pads arranged on a surface of the carrier structure, and a plurality of bonding wires are connected to a plurality of electrode pads of the electronic element and the plurality of wire-bonding pads. Further, among any three adjacent ones of the plurality of wire-bonding pads, a long-distanced first wire-bonding pad, a middle-distanced second wire-bonding pad and a short-distanced third wire-bonding pad are defined according to their distances from the electronic element. Therefore, even if the bonding wires on the first to third wire-bonding pads are impacted by an adhesive where a wire sweep phenomenon occurred when the flowing adhesive of a packaging layer covers the electronic element and the bonding wires, the bonding wires still would not contact each other, thereby avoiding short circuit problems.

A semiconductor device being capable of high-speed data transmission and having a reduced circuit area is provided. The semiconductor device includes a semiconductor chip, an external terminal, and a layer including two facing surfaces. The semiconductor chip is provided on one surface side of the layer, and the external terminal is provided on the other surface side of the layer at least in a region not overlapping with the semiconductor chip. The semiconductor chip includes a first circuit including a first transistor, and the layer includes a second circuit including a second transistor. The first circuit is electrically connected to the second circuit, and the second circuit is electrically connected to the external terminal. The second transistor includes a metal oxide in a channel formation region. Note that the second circuit may be a CML circuit. In addition, an insulator may be provided above the one surface of the layer and on a side surface of the semiconductor chip.