A semiconductor package includes a semiconductor chip including a semiconductor substrate having an active layer, ground chip pads on the semiconductor substrate, and signal chip pads on the semiconductor substrate and a package substrate supporting the semiconductor chip, the package substrate including a substrate insulating layer, a plurality of signal line patterns extending in the substrate insulating layer and electrically connected to the signal chip pads, and a plurality of ground line patterns extending in the substrate insulating layer at a same level as a level of the plurality of signal line patterns and electrically connected to the ground chip pads. At least one of the plurality of ground line patterns extends between the plurality of signal line patterns.

A header for a semiconductor package, includes an eyelet having a through hole penetrating the eyelet from an upper surface to a lower surface of the eyelet, a first lead inserted inside the through hole, and an insulating substrate disposed on the upper surface of the eyelet, and provided with a first through hole at a position overlapping one end of the first lead in a plan view. The insulating substrate has a thermal conductivity lower than a thermal conductivity of the first lead. A first conductive layer is formed on an inner wall defining the first through hole, and the first conductive layer extends to an upper surface of the insulating substrate. The one end of the first lead is electrically connected to the first conductive layer, and a space is provided above the one end of the first lead inside the first through hole.

A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.

An integrated circuit chip includes; a package substrate including a first signal ball, a first semiconductor chip on the package substrate, a second semiconductor chip on the first semiconductor chip, a first bump disposed between the package substrate and the first semiconductor chip and electrically connected to the first signal ball, and a second bump disposed between the first semiconductor chip and the second semiconductor chip and electrically connected to the first signal ball, wherein during a first mode, the first signal ball receives a signal from the first semiconductor chip through the first bump and receives a signal from the second semiconductor chip through the second bump.

A method of forming a semiconductor package includes providing a semiconductor die that includes a bond pad disposed at an upper side of the semiconductor die, providing a carrier that includes a die attach pad and a landing pad, mounting the semiconductor die on the die attach pad with the bond pad facing away from the carrier, and attaching an electrical interconnect element between the bond pad and the landing pad, wherein the bond pad is formed from nanowires.

Provided is a semiconductor package including a plurality of first semiconductor chips respectively including a first semiconductor substrate and a plurality of first through electrodes penetrating the first semiconductor substrate, a second semiconductor chip on the plurality of first semiconductor chips, the second semiconductor chip including a second semiconductor substrate and a plurality of second through electrodes penetrating the second semiconductor substrate, a third semiconductor chip on the second semiconductor chip, the third semiconductor chip including a third semiconductor substrate and a plurality of third through electrodes penetrating the third semiconductor substrate, and a first encapsulation material on the plurality of first semiconductor chips, a planar shape of the second semiconductor chip is greater than a planar shape of each first semiconductor chip of the plurality of first semiconductor chips, and a planar shape of the third semiconductor chip is greater than the planar shape of the second semiconductor chip.

A semiconductor package includes a first semiconductor chip, a sealing layer molding the first semiconductor chip, and an upper connection structure on the sealing layer, wherein the upper connection structure includes an insulating layer. The insulating layer includes marking patterns defined by a first region and a second region, the first region being at at least a portion of the insulating layer and having a first light transmittance value, the second region being at at least a portion of the first region and having a second light transmittance value different from the first light transmittance value.

An integrated circuit package structure is provided. The integrated circuit package structure includes a circuit substrate. The circuit substrate includes a core, a first inorganic dielectric layer, an organic dielectric layer and a solder mask layer. The core has a first surface and a second surface opposite each other. The first inorganic dielectric layer is disposed on the first surface of the core. The organic dielectric layer is disposed on the second surface of the core. The solder mask layer is disposed on the organic dielectric layer. The solder mask is separated from the first inorganic dielectric layer by the organic dielectric layer and the core.

A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

In an embodiment, a device includes: a first integrated circuit die comprising a semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first integrated circuit die, a surface of the gap-fill dielectric being substantially coplanar with an inactive surface of the semiconductor substrate and with a surface of the first through-substrate via; a dielectric layer on the surface of the gap-fill dielectric and the inactive surface of the semiconductor substrate; a first bond pad extending through the dielectric layer to contact the surface of the first through-substrate via, a width of the first bond pad being less than a width of the first through-substrate via; and a second integrated circuit die comprising a die connector bonded to the first bond pad.