A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a first upper pad arranged on an upper surface of the first semiconductor substrate, a first polymer layer arranged on the upper surface of the first semiconductor substrate, a second semiconductor chip mounted on the first semiconductor chip, the second semiconductor chip including a second semiconductor substrate and a second lower pad arranged under a lower surface of the second semiconductor substrate, wherein the first polymer layer has a horizontal width in a direction crossing the first polymer layer in a center region of the second semiconductor chip, as a first length, and has a horizontal width in a direction crossing two corner regions of the first polymer layer in corner regions of the second semiconductor chip, as a second length, wherein the second length is greater than the first length.

Provided is a semiconductor package with improvement in warpage thereof and a method of fabricating the semiconductor package. The semiconductor package includes a first semiconductor chip, a redistribution substrate on the first semiconductor chip, a second semiconductor chip on the redistribution substrate, a first encapsulant encapsulating the second semiconductor chip, on the redistribution substrate, a metal post arranged on a top surface of the first semiconductor chip, and a second encapsulant covering side surfaces of the metal post, on the bottom surface of the first semiconductor chip.

A chip stacking structure includes: a first chip, a second chip stacked with the first chip, a first redistribution layer, a second redistribution layer, a third redistribution layer, a first conductive channel, and a second conductive channel; the first redistribution layer is disposed on a surface of the first chip facing the second chip; the second redistribution layer is disposed on a passive surface of the second chip, and the third redistribution layer is disposed on an active surface of the second chip; the first conductive channel passes through the second chip and the third redistribution layer, connecting the first redistribution layer and the second redistribution layer; and the second conductive channel passes through the second chip, connecting the second redistribution layer and the third redistribution layer.

A display device can include a base part; first electrodes which extend in one direction and which are formed on the base part at certain intervals; an insulating layer formed on the base part to cover the first electrodes; second electrodes which extend in the same direction as the first electrodes and which are formed on the insulating layer so as to be arranged between the first electrodes; a partition part stacked on the insulating layer and the second electrodes while forming assembly holes so as to be overlapped on the first electrodes and the second electrodes; semiconductor light-emitting elements placed in the assembly holes; and third electrodes arranged on the partition part. The semiconductor light-emitting elements are not electrically connected to the first electrodes and are electrically connected to the second electrodes and the third electrodes.

A semiconductor package includes a plurality of first semiconductor dies, a first bonding layer, a redistribution layer, a plurality of second semiconductor dies and a plurality of conductive terminals. The first bonding layer is disposed on the first semiconductor dies, and includes a plurality of first bonding pads. The redistribution layer is disposed on and electrically connected to the first bonding pads. The second semiconductor dies are disposed on and electrically connected to the redistribution layer, wherein backside surfaces of the second semiconductor dies are facing active surfaces of the first semiconductor dies. The conductive terminals are disposed on and electrically connected to the second semiconductor dies.

Disclosed are semiconductor packages. A semiconductor package may include a first die encapsulated by a mold, and a second die directly on the mold. One or more conductive posts may be formed in the mold. A frontside redistribution layer (RDL) may be provided on a lower surface of the mold. Electrical signals between the first and second dies may be carried through the posts and the frontside RDL. There is no need for backside RDL and backside ball grid array. This can significantly reduce the height of the semiconductor package.

A method of forming a semiconductor device is provided. The method include forming an interposer having a first set of conductive connection pads exposed at a first major side of an interposer substrate and a second set of conductive connection pads exposed at a second major side of the interposer substrate. A first semiconductor wafer is mounted on the first major side of the interposer substrate and a second semiconductor wafer is mounted on the second major side of the interposer substrate. A sandwich-like structure is formed by the first semiconductor wafer, interposer, and second semiconductor wafer. The sandwich-like structure is singulated to form a plurality of individual semiconductor device units. A plurality of sidewall connection pads are exposed along an outer perimeter of the interposer.

A display device includes a first conductive layer including a first voltage line and a second voltage line, a buffer layer, a semiconductor layer including a first active layer and a second active layer, a first gate insulating layer, a second conductive layer including a first gate electrode overlapping the first active layer and a second gate electrode overlapping the second active layer, a passivation layer, a via layer, a bank pattern layer including a first bank pattern and a second bank pattern partially spaced apart from each other, a third conductive layer including a first electrode and a second electrode spaced apart from each other, and light emitting elements. The passivation layer includes silicon nitride (SiN.sub.x), and a ratio of a number of silicon-hydrogen bonds (SiH) to a number of nitrogen-hydrogen bonds (NH) in the silicon nitride (SiN.sub.x) is in a range of about 1:0.6 to about 1:1.5.

A display device includes: a substrate; a plurality of pixel columns on the substrate, each of the plurality of pixel columns including a plurality of pixel groups each including a first pixel and a second pixel arranged along a first direction; and a bank enclosing a perimeter of each of the plurality of pixel groups, the bank including a first opening corresponding to each of the plurality of pixel groups, and a second opening located between two pixel groups adjacent to each other in the first direction among the plurality of pixel groups.

An isolator includes a substrate, a first chip, and a second chip. The substrate includes an insulation layer and a pair of coils. The pair of coils are opposite to each other in a thickness direction via the insulation layer. The first chip is disposed to face one surface of the substrate. The first chip is connected to one of the pair of coils. The second chip is disposed to face the other surface of the substrate. The second chip is connected to the other of the pair of coils.