A chip production method in which a workpiece having a plurality of planned dividing lines set on a side of a front surface of a substrate and a functional layer formed on the front surface is divided along the planned dividing lines to produce chips, includes: applying a laser beam along the planned dividing lines to remove respective parts of the functional layer and form, in the substrate, respective processed grooves having a depth smaller than a finished thickness; processing a side of a back surface of the substrate to thin the substrate to the finished thickness; and after the processing, imparting an external force to the workpiece to divide the workpiece into a plurality of chips along the processed grooves.

A wafer transfer method for forming a second work unit by transferring a wafer of a first work unit including a first ring frame, a first adhesive tape, and the wafer to a second adhesive tape includes sandwiching a claw body between the first ring frame and a second ring frame, affixing the second adhesive tape to a surface of the wafer which surface is not affixed to the first adhesive tape, holding the wafer by the second ring frame via the second adhesive tape, and peeling off the first adhesive tape from the wafer.

A method of fabricating a semiconductor package includes preparing a semiconductor device including a plurality of step structures, covering, at a first temperature, a portion of the plurality of step structures with a fixing film, fixing the fixing film on the portion of the plurality of step structures by performing, at a second temperature, an annealing process on the fixing film, and separating, at a third temperature, at least a portion of the fixing film from the semiconductor device. Each of the first temperature and the third temperature is greater than the second temperature. The fixing film includes a paraffin-based compound. The fixing film at each of the first temperature and the third temperature has an elastic modulus less than an elastic modulus of the fixing film at the second temperature.

A semiconductor packaging structure includes an encapsulation layer, a die, a first metal layer, a second metal layer and an electrical connection component. The die is disposed in the encapsulation layer. The first metal layer and the second metal layer are disposed in the encapsulation layer. The first metal layer and the second metal layer are disposed on opposite sides of the die, respectively. The electrical connection component is disposed in the encapsulation layer. The first metal layer is electrically connected with the second metal layer through the electrical connection component. The electrical connection component includes a non-metal core and a metal film located on a surface of the non-metal core.

A laminate substrate is divided along a plurality of intersecting scheduled division lines. The laminate substrate has a first substrate and a second substrate formed of the same material, laminated through an intermediate layer containing metal. The laminate substrate is divided by cutting the laminate substrate along the scheduled division lines by use of a substrate cutting blade to form the first substrate with first cut grooves each having a width larger than a cutting edge thickness of a metal cutting blade which is larger in cutting edge thickness than the substrate cutting blade, and thereafter cutting the laminate substrate along the first cut grooves by use of the metal cutting blade to cut the intermediate layer and to form second cut grooves each having a width corresponding to the cutting edge thickness of the metal cutting blade.

An accelerated test for applying a high voltage is performed without reducing a manufacturing yield of a semiconductor device using a wide gap semiconductor material. The technical idea in the embodiment is, for example, an idea of performing the accelerated test in the state of a semiconductor wafer to distinguish a latent defect as illustrated in FIG. 4. That is, the technical idea in the embodiment is to perform the accelerated test on a semiconductor chip containing a wide bandgap semiconductor material as a main component not in the state of a semiconductor chip but in the state of the semiconductor wafer.

A heterogeneous epitaxial structure formed on a SiC (silicon carbide) substrate. An intermediate layer comprising AIN is formed overlying the SiC substrate. The surface of the intermediate layer comprises AIN formed by lateral epitaxial growth. The lateral epitaxial growth merges to form the surface comprising a MELO layer (merged epitaxial lateral overgrowth). The intermediate layer includes a carbon layer underlying the MELO layer. At least one device layer comprising GaN (gallium nitride) is formed overlying the surface of the intermediate layer in which one or more semiconductor devices are formed. The carbon layer is heated to fracture portions of the intermediate layer to separate the SiC substrate from the intermediate layer. The SiC substrate is not consumed by the separation thereby allowing perpetual reuse in semiconductor wafer processing.

A protective tape peeling apparatus may include a support table to support wafers having respective protective tapes attached thereto; a roller holder having an upper pinch roller and a lower pinch roller to move the protective tape peeled off from a wafer therebetween; an attachment portion to attach one end of the protective tape between the upper and lower pinch rollers to a first protective tape attached to a first wafer on the support table, and attach one end of the first protective tape between the upper pinch roller and the lower pinch roller to a second protective tape attached to a second wafer on the support table; and a reversing guide to reverse a non-adhesive surface of one end of the first protective tape between the upper and lower pinch rollers to face the support table when the roller holder moves from a first position to a second position.

A semiconductor package includes: a substrate including a first region and a second region at least partially surrounding the first region in a plane defined by first and second horizontal directions, wherein the substrate has a first surface and a second surface opposed to the first surface; a wiring pattern disposed on the first surface of the substrate; a first recess formed on the second surface of the substrate and in the second region of the substrate; a back side insulating layer disposed on the second surface of the substrate, wherein the back side insulating layer fills an inside of the first recess; a through via penetrating through the first region of the substrate and the back side insulating layer, wherein the through via connects to the wiring pattern; and a second recess formed in the back side insulating layer and on the first recess.

A die bonding method is disclosed, through coating bonding adhesive on front side of device wafer and bonding carrier wafer thereto, back-side connection structure can be formed on back side of device wafer to lead out an interconnect structure in device wafer to back side of device wafer, and dies thereon can be bonded at front sides to target wafer. Moreover, after device wafer is debonded from carrier wafer, the bonding adhesive is retained on front side of device wafer to provide protection to front side of device wafer during subsequent dicing of device wafer, and to avoid particles or etching by-products produced during dicing process from adhering to front side of device wafer. Such etching by-products are subsequently removed along with the bonding adhesive, ensuring cleanness of front sides of individual dies resulting from dicing process and improved quality of bonding of dies at front sides to target wafer.