H10W70/479

Wire bonded semiconductor device package
12519054 · 2026-01-06 · ·

In a described example, an apparatus includes: a metal leadframe including a dielectric die support formed in a central portion of the leadframe, and having metal leads extending from the central portion, portions of the metal leads extending into the central portion contacted by the dielectric die support; die attach material over the dielectric die support; a semiconductor die mounted to the dielectric die support by the die attach material, the semiconductor die having bond pads on a device side surface facing away from the dielectric die support; electrical connections extending from the bond pads to metal leads of the leadframe; and mold compound covering the semiconductor die, the electrical connections, the dielectric die support, and portions of the metal leads, the mold compound forming a package body.

Semiconductor module
12525527 · 2026-01-13 · ·

A module arrangement for power semiconductor devices, includes two or more heat spreading layers with a first surface and a second surface being arranged opposite to the first surface. At least two or more power semiconductor devices are arranged on the first surface of the heat spreading layer and electrically connected thereto. An electrical isolation stack comprising an electrically insulating layer and electrically conductive layers is arranged in contact with the second surface of each heat spreading layer. The at least two or more power semiconductor devices, the heat spreading layers and a substantial part of each of the electrical isolation stacks are sealed from their surrounding environment by a molded enclosure. Accordingly, similar or better thermal characteristic of the module can be achieved instead of utilizing high cost electrically insulating layers, and double side cooling configurations can be easily implemented, without the use of a thick baseplate.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
20260033338 · 2026-01-29 · ·

A semiconductor device, including: a stacked substrate; a semiconductor device element mounted on the stacked substrate via a first bonding layer; a metal base bonded to the stacked substrate via a second bonding layer; and a water jacket bonded to the metal base, the water jacket having two ends and a center portion. The first and second bonding layers are identical, or different, in a material and a composition thereof. The water jacket has a plurality of heat dissipation fins, lengths of which are in an ascending order from each of the ends of the water jacket to the center portion of the water jacket.

Power Module

According to the present disclosure, upper and lower substrates may be electrically connected to a lead frame, such that wire bonding may be excluded, and electrical connection and heat dissipation may be performed without a spacer by improving a connection structure in the upper and lower substrates. In addition, a power module is introduced in which because a spacer for forming a large current path may be excluded, a current path may be shortened, such that power performance may be improved, an internal space may be additionally provided, costs may be reduced, and an overall size of the power module may be reduced.

Power Module

In the present disclosure, a central substrate is additionally disposed between an upper and lower substrates, thereby simplifying a current loop of a module. In addition, by simplifying the current loop between the upper and lower substrates, the central substrate enhances current overlap effect. Further disclosed is a power module in which an insulating pattern and a via spacer to form the current loop are reduced in size, resulting in a reduction of the overall module size.

Method for manufacturing busbar assembly
12562557 · 2026-02-24 · ·

According to a manufacturing method of the present invention, it is possible to manufacture a busbar assembly in an efficient manner, the busbar assembly including busbars disposed in parallel in a common plane and an insulative resin layer including a gap filling portion filled into a gap between the adjacent busbars and a bottom-surface-side laminated portion extending integrally from the gap filling portion and arranged on bottom surfaces of the busbars, a top surface of the busbar being at least partially exposed to form a top-surface-side connection portion, the bottom surface of the busbar including a first bottom surface region which is located at the same position in a thickness direction as a lower end portion of the gap and on which the bottom-surface-side laminated portion is arranged and a second bottom surface region located farther away from the top surface than the first bottom surface region and exposed to the outside to form a bottom-surface-side connection portion.

SEMICONDUCTOR DEVICE
20260053029 · 2026-02-19 ·

A semiconductor device includes a substrate, a conductive part formed on a front surface of the substrate, a semiconductor chip disposed on the front surface of the substrate, a control unit that controls the semiconductor chip, a sealing resin that covers the semiconductor chip, the control unit and the conductive part, and a first lead bonded to the conductive part and partially exposed from the sealing resin. The conductive part includes a first pad and a second pad disposed apart from each other. The first lead is bonded to the first pad and the second pad.

Lead frame, chip package structure, and manufacturing method thereof

A method of forming a lead frame can include: providing a frame base; providing a substrate to support the frame base; and selectively etching the frame base to form first and second type pins. The first type pins are distributed in the central area of the lead frame, and the second type of the pins are distributed in the edge area of the lead frame. The first type pins are separated from the second type of the pins, and the first and second type pins are not connected by connecting bars. A pattern of a first surface of the first and second type pins is different from that of a second surface of the first and second type pins. The metal of the first surface is different from the metal of the second surface, and the second surface is opposite to the first surface.

Wireless transistor outline package structure

A wireless transistor outline (TO) package structure includes a carrying module, a chip and a lead frame both mounted on the carrying module, a sheet-like bonding module mounted on the chip and the lead frame in a flip chip manner, and an encapsulant that covers the above components therein. A connection pad of the chip and a connection segment of the lead frame are coplanar with each other. The sheet-like bonding module includes a ceramic substrate and a plurality of circuit layers that are stacked and formed on the ceramic substrate in a direct plated copper (DPC) manner. Areas of the circuit layers gradually decrease in a direction away from the ceramic substrate, and thicknesses of the circuit layers gradually increase in the same direction. The circuit layer arranged away from the ceramic substrate connects the connection pad and the connection segment for establishing an electrical connection therebetween.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
20260047450 · 2026-02-12 ·

A semiconductor device includes a support member, a semiconductor element and a sealing member. The semiconductor element is disposed on a first side in a thickness direction relative to the support member. The sealing member covers a part of the support member and the semiconductor element. The support member has a first surface facing a second side in the thickness direction and exposed from the sealing member. The first surface is formed with a first uneven region. In an example, the first uneven region has an arithmetic mean roughness between 0.2 m and 13 m. In an example, the first uneven region includes a plurality of uneven lines in an arc shape.