H10W72/354

PACKAGE STRUCTURE AND PACKAGE METHOD

A package structure includes a substrate having conductive lines along a direction parallel to a surface of the substrate, and an optoelectronic chip bonded on the first substrate. A part of areas of the substrate is a first substrate, and remaining areas of the substrate are a second substrate. A base material of the first substrate is a light-transparent material, the first substrate has the conductive lines, and a base material of the second substrate is a non-light-transparent material. An active area of the optoelectronic chip is oriented toward the first substrate. The active area is arranged staggered with the conductive lines in the first substrate, and the optoelectronic chip is electrically connected with the conductive lines in the first substrate.

SYSTEMS AND METHODS FOR DIRECT BONDING IN SEMICONDUCTOR DIE MANUFACTURING
20260040985 · 2026-02-05 ·

A method for bonding semiconductor dies, resulting semiconductor devices, and associated systems and methods are disclosed. In some embodiments, the method includes depositing a first material on the first semiconductor die. The first material has a first outer surface and a first chemical composition at the first outer surface. The method also includes depositing a second material on the second semiconductor die. The second material has a second outer surface and a second chemical composition at the second outer surface that is different from the first chemical composition. The method also includes stacking the dies. The second outer surface of the second semiconductor die is in contact with the first outer surface of the first semiconductor die in the stack. The method also includes reacting the first outer surface with the second outer surface. The reaction causes the first outer surface to bond to the second outer surface.

ISOLATION FOR CHIP ON LEAD DEVICE AND MANUFACTURING METHOD
20260040958 · 2026-02-05 ·

An electronic device includes a conductive lead, a semiconductor die, a package structure enclosing the semiconductor die and a portion of the conductive lead, and a non-conductive die attach film extending between the conductive lead and the semiconductor die and having a thickness less than 50 m. A method of fabricating an electronic device includes singulating portions of a non-conductive die attach film on a carrier, partially singulating prospective die areas from a front side of a wafer, removing wafer material from a back side of the wafer to separate a semiconductor die from the wafer, and attaching a backside the semiconductor die to a singulated portion of the non-conductive die attach film on the carrier.

Bottom package exposed die MEMS pressure sensor integrated circuit package design

A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound.

Thermally conductive material for electronic devices

An electrically non-conducting film (109) comprising an oligomer comprising an arylene or heteroarylene repeating unit is disposed between a chip (105), e.g. a flip-chip, and a functional layer (101), e.g. a printed circuit board, electrically connected to the chip by electrically conducting interconnects (107). The oligomer may be crosslinked.

Silver particles, method for producing silver particles, paste composition, semiconductor device, and electrical and/or electronic components
12539539 · 2026-02-03 · ·

Provided are silver particles including a silver powder and a silver layer that includes primary particles, the primary particles being smaller than the silver powder.

Silver nanoparticles synthesis method for low temperature and pressure sintering

The disclosure is directed to wide band-gap semiconductor devices, such as power devices based on silicon carbide or gallium nitride materials. A power device die is attached to a carrier substrate or a base using sintered silver as a die attachment material or layer. The carrier substrate is, in some embodiments, copper plated with silver. The sintered silver die attachment layer is formed by sintering silver nanoparticle paste under a very low temperature, for example, lower than 200 C. and in some embodiments at about 150 C., and with no external pressures applied in the sintering process. The silver nanoparticle is synthesized through a chemical reduction process in an organic solvent. After the reduction process has completed, the organic solvent is removed through evaporation with a flux of inert gas being injected into the solution.

Sintering paste and use thereof for connecting components

The invention relates to a sintering paste consisting of: (A) 30 to 40 wt. % of silver flakes with an average particle size ranging from 1 to 20 m, (B) 8 to 20 wt. % of silver particles with an average particle size ranging from 20 to 100 nm, (C) 30 to 45 wt. % of silver(I) oxide particles, (D) 12 to 20 wt. % of at least one organic solvent, (E) 0 to 1 wt. % of at least one polymer binder, and (F) 0 to 0.5 wt. % of at least one additive differing from constituents (A) to (E).

Semiconductor device and semiconductor device manufacturing method
12543591 · 2026-02-03 · ·

According to one embodiment, a semiconductor device includes: a circuit board; a first semiconductor chip mounted on a face of the circuit board; a resin film covering the first semiconductor chip; and a second semiconductor chip having a chip area larger than a chip area of the first semiconductor chip, the second semiconductor chip being stuck to an upper face of the resin film and mounted on the circuit board. The resin film entirely fits within an inner region of a bottom face of the second semiconductor chip when viewed in a stacking direction of the first and second semiconductor chips.

Semiconductor devices and methods of forming the same

Semiconductor devices including the use of solder materials and methods of manufacturing are provided. In embodiments the solder materials utilize a first tensile raising material, a second tensile raising material, and a eutectic modifier material. By utilizing the materials a solder material can be formed and used with a reduced presence of needles that may otherwise form during the placement and use of the solder material.