A semiconductor structure includes an interposer including redistribution wiring interconnects and redistribution insulating layers; a first semiconductor die attached to the interposer through a first array of solder material portions; and a second semiconductor die attached to the interposer through a second array of solder material portions. The interposer includes at least one inductor structure located between an area of the first array of solder material portions and an area of the second array of solder material portions in a plan view and laterally encloses a respective area in the plan view.

A three-dimensional fan-out integrated package structure, a packaging method thereof, and a wireless headset are disclosed. The three-dimensional fan-out integrated package structure includes a first rewiring layer, a second rewiring layer, a metal connection pillar, a first semiconductor chip, a second semiconductor chip, a first filler layer, a first encapsulating layer, a functional chip, a second filler layer, a second encapsulating layer, and metal bumps. By stacking two semiconductor chips, the structure can effectively reduce the packaging area and realize device packaging with high density and high integration, while enabling the minimum line width/line spacing to be reduced to 1.5 m/1.5 m. In addition, the three-dimensional fan-out integrated package structure can simultaneously integrate various functional chips and components such as GPU/PMU/DDR/mm-wave antenna/capacitor/inductor/transistor/flash memory/filter to realize system-level packaging, which not only can reduce cost but also improve the effectiveness of the package structure by using physical isolation to reduce device interference.

Provided is a semiconductor package including a substrate including a mounting region, a first dam surrounding at least a portion of the mounting region, and a second dam spaced apart from the first dam and surrounding the first dam, a sub-semiconductor package on the mounting region of the substrate, conductive bumps between the substrate and the sub-semiconductor package and electrically connecting the substrate and the sub-semiconductor package, and an underfill material filling at least a portion of a space between the substrate and the sub-semiconductor package, and covering the conductive bumps, wherein the first dam and the second dam protrude upward from one surface of the substrate, and an inner wall surface of the first dam includes an inclined surface extending in a direction away from the second dam such that a distance from the second dam to the inclined surface increases as the inner wall surface extends downward.

An example chip packaging structure includes a redistribution layer, and the redistribution layer includes a first copper pillar layer, a second copper pillar layer, and a metal routing layer. The first copper pillar layer includes a plurality of first copper pillars, and the second copper pillar layer includes a plurality of second copper pillars. The metal routing layer is located between the first copper pillar layer and the second copper pillar layer, and the metal routing layer is electrically connected to the plurality of first copper pillars and the plurality of second copper pillars. The plurality of first copper pillars are coplanar on a first side close to the metal routing layer, and the plurality of second copper pillars are coplanar on a second side away from the metal routing layer.

The present invention provides a curable resin having excellent dielectric properties, a curable resin composition, and cured products thereof. The present invention specifically provides a curable resin which is represented by formula (1). In formula (1), A represents any of the following formulas (1-a) to (1-d). The plurality of X each independently represent any of the following formulas (1-e) to (1-g). The plurality of R.sub.1 each independently represent a residue obtained by removing one hydrogen atom from a C9 petroleum resin. The plurality of R.sub.2 each independently represent a hydrogen atom, a hydrocarbon group having 1 to 10 carbon atoms, an alkoxy group having 1 to 6 carbon atoms, an amino group, or a hydroxy group. The plurality of s and t are each independently an integer of 0 to 3, and the total of s, which is the number of R.sub.1 moieties, and t, which is the number of R.sub.2 moieties, the moieties being bonded to the same aromatic ring, is an integer of 0 to 3. The average value of s s.sub.ave satisfies 0<s.sub.ave3, and the average value of t t.sub.ave satisfies 0t.sub.ave2. n is the average number of repetitions and satisfies 0.1n5.

##STR00001##

The present invention provides a curable resin having excellent dielectric properties, a curable resin composition, and cured products thereof. The present invention specifically provides a curable resin which is represented by formula (1). In formula (1), A represents any of the following formulas (1-a) to (1-d). The plurality of X each independently represent any of the following formulas (1-e) to (1-g). The plurality of R.sub.1 each independently represent a residue obtained by removing one hydrogen atom from a C9 petroleum resin. The plurality of R.sub.2 each independently represent a hydrogen atom, a hydrocarbon group having 1 to 10 carbon atoms, an alkoxy group having 1 to 6 carbon atoms, an amino group, or a hydroxy group. The plurality of s and t are each independently an integer of 0 to 3, and the total of s, which is the number of R.sub.1 moieties, and t, which is the number of R.sub.2 moieties, the moieties being bonded to the same aromatic ring, is an integer of 0 to 3. The average value of s s.sub.ave satisfies 0<s.sub.ave3, and the average value of t t.sub.ave satisfies 0t.sub.ave2. n is the average number of repetitions and satisfies 0.1n5.

##STR00001##

An integrated circuit (IC) package comprises: at least two substrate sub-units configured to adjoin each other to form a substrate, each substrate sub-unit comprising electrical traces configured to couple i) to corresponding terminals of an integrated circuit component and ii) to corresponding terminals of an interposer or a printed circuit board; at least one coupler configured to: 1) align the substrate sub-units and 2) join the substrate sub-units together to form the substrate from the at least two substrate sub-units; and, an integrated circuit having terminals and configured to electrically couple to terminals of the substrate formed of at least two substrate sub-units.

Some embodiments relate to a package. The package includes a first substrate, a second substrate, and an interposer frame between the first and second substrates. The first substrate has a first connection pad disposed on a first face thereof, and the second substrate has a second connection pad disposed on a second face thereof. The interposer frame is arranged between the first and second faces and generally separates the first substrate from the second substrate. The interposer frame includes a plurality of through substrate holes (TSHs) which pass entirely through the interposer frame. A TSH is aligned with the first and second connection pads, and solder extends through the TSH to electrically connect the first connection pad to the second connection pad.

A power module includes a heat dissipation substrate, a carrier, a connection substrate, a power transistor chip group, a plurality of conductive members, a plurality of external connection leads, and a package. The carrier is disposed on the heat dissipation substrate and includes an insulation plate and a patterned metal circuit layer. The connection substrate is disposed on the patterned metal circuit layer and includes a multilayered metallic connection structure. The power transistor chip group is disposed on the connection substrate and includes a plurality of power transistor chips electrically connected to one another through the multilayered metallic connection structure. The conductive members are electrically connected to the patterned metal circuit layer of the carrier. The external connection leads are disposed on the patterned metal circuit layer. The package packages the heat dissipation substrate, the carrier, the connection substrate, the power transistor chip group, and the external connection leads.