A package substrate based on a molding process may include an encapsulation layer, a support frame located in the encapsulation layer, a base, a device located on an upper surface of the base, a copper boss located on a lower surface of the base, a conductive copper pillar layer penetrating the encapsulation layer in the height direction, and a first circuit layer and a second circuit layer over and under the encapsulation layer. The second circuit layer includes a second conductive circuit and a heat dissipation circuit, the first circuit layer and the second conductive circuit are connected conductively through the conductive copper pillar layer, the heat dissipation circuit is connected to one side of the device through the copper boss and the base, and the first circuit layer is connected to the other side of the device.

The technology of this application relates to a packaging module and a packaging method therefor, and an electronic device. The packaging module includes at least two device groups and a shielding structure configured to shield the at least two device groups. The shielding structure includes a partition structure configured to perform electromagnetic isolation between every two adjacent device groups. The partition structure includes a plurality of conductive pillars and conductive adhesive, and a conductivity of the conductive pillar is greater than a conductivity of the conductive adhesive. The plurality of conductive pillars are arranged at intervals and are electrically connected to a ground layer of a substrate, the conductive adhesive fills a gap between any adjacent conductive pillars, and any adjacent conductive pillars are electrically connected by using the conductive adhesive.

A semiconductor die assembly is introduced in this disclosure. The semiconductor die assembly includes one or more semiconductor dies, a dielectric layer disposed under a bottom surface of the one or more semiconductor dies, and metal fragments or a metal layer disposed under the dielectric layer, wherein metal-OH bonds or metal-OSiOH bonds are disposed on a bottom surface of the dielectric layer. Alternatively, the semiconductor die assembly includes one or more semiconductor dies, a metal layer disposed under a bottom surface of the one or more semiconductor dies, and a metal oxidation layer disposed under the dielectric layer, wherein the metal oxidation layer comprises metal-OH bonds or metal-OSiOH bonds.

A semiconductor die is arranged at a mounting region of a surface of a substrate. A substrate includes electrically conductive leads around a die pad including a mounting region. A metallic layer is located at one or more portions of the substrate including the mounting region. A semiconductor die is arranged at a mounting region. The metallic layer is selectively exposed at portions less than all of the metallic layer to an oxidizing plasma to produce a patterned oxide layer including oxides of metallic material in the metallic layer. An electrically insulating encapsulation is molded onto the surface of the substrate to encapsulate the semiconductor die. The oxides of metallic material in the patterned oxide layer facilitate adhesion of the electrically insulating encapsulation to the surface of the substrate.

In a method of manufacturing a semiconductor package, at least one conductive wire is formed on a substrate in a wire bonding process, a ball end of the conductive wire is located above the substrate, a molding material is provided to cover the conductive wire except the ball end, and an EMI shielding layer is formed on the molding material to connect to the ball end. Owing to the ball end is exposed on the molding material, connection area of the EMI shielding layer to the conductive wire is increased to improve connection strength and reliability between the EMI shielding layer and the conductive wire.

A method of forming a semiconductor structure includes: forming a first redistribution structure on a first side of a wafer, the first redistribution structure including dielectric layers and conductive features in the dielectric layers; forming grooves in the first redistribution structure, the grooves exposing sidewalls of the dielectric layers and the wafer, the grooves defining a plurality of die attaching regions; bonding a plurality of dies to the first redistribution structure in the plurality of die attaching regions; forming a first molding material on the first side of the wafer around the plurality of dies, the first molding material filling the grooves; forming a passivation layer on a second side of the wafer opposing the first side; and dicing along the grooves from the second side of the wafer to form a plurality of individual semiconductor packages, each of the plurality of individual semiconductor packages including a respective die.

A semiconductor package includes a semiconductor element, a first insulating layer, a first wiring layer, a second insulating layer, and a second wiring layer. The first insulating layer covers the semiconductor element. The first wiring layer includes a first layer section. The first layer section covers the first insulating layer. The second insulating layer covers the first insulating layer and the first wiring layer. The second wiring layer is electrically connected to the semiconductor element through a second through hole and a third through hole. The second wiring layer includes a second layer section. The second layer section covers the second insulating layer. The second layer section of the second wiring layer has a portion overlying the first layer section of the first wiring layer with the second insulating layer interposed.

A semiconductor device, including a cooling body, a semiconductor unit including a wiring portion electrically connected to a semiconductor chip, and a sealing member sealing the entire semiconductor unit over a cooling surface of the cooling body. The sealing member includes a first portion and a second portion which surrounds the first portion in a plan view. The first portion seals a central portion of a main electrode of the semiconductor chip, and has a first sealing surface opposite the cooling surface of the cooling body. The second portion seals a wiring portion to thereby surround the first portion in the plan view, and has a second sealing surface opposite the cooling surface. A distance in a thickness direction of the semiconductor device from the cooling surface to the first sealing surface, is smaller than a distance in the thickness direction from the cooling surface to the second sealing surface.

A packaging structure and methods of forming the same are described. In some embodiments, the structure includes a through via, a first semiconductor die disposed adjacent the through via, a stress relief layer disposed on side surfaces of the through via and side surfaces of the first semiconductor die, and a molding material disposed on the stress relief layer and between the through via and the first semiconductor die. Top surfaces of the through via, the semiconductor die, and the molding material are substantially coplanar.

A package and method is disclosed. In one example, the package comprises a carrier comprising a component mounting area from which a tie bar extends, the tie bar being configured for being clamped by an encapsulation tool pin during encapsulation, an electronic component mounted on the component mounting area, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier, wherein a sidewall of the package has a step between a first vertical sidewall section and a second vertical sidewall section; wherein the first vertical sidewall section has a notch in the encapsulant and a part of the second vertical sidewall section exposes the tie bar.