A method of determining a height value of a wire loop on a wire bonding machine is provided. The method includes the steps of: (a) imaging at least a portion of a wire loop using an imaging system on a wire bonding machine to detect a path of the portion of the wire loop; (b) moving a wire bonding tool towards a first contact portion of the wire loop in the path; (c) detecting when a portion of a conductive wire engaged with the wire bonding tool contacts the first contact portion of the wire loop; and (d) determining a height value of the wire loop at the first contact portion based on a position of the wire bonding tool when the portion of the conductive wire contacts the first contact portion of the wire loop.

A semiconductor device includes a semiconductor die having a die surface, in which the die surface includes a bond pad. A ball bond has a distal surface and flattened-disk shape extending from the distal surface and terminating in a proximal surface spaced apart from the distal surface. The distal surface is coupled to the bond pad and a channel extends a depth into the proximal surface surrounding a central portion of the proximal surface. A bond wire extending from the central portion of the proximal surface, in which the channel is spaced apart from and surrounds the bond wire.

A bonding apparatus configured to bond substrates includes a first holder configured to vacuum-exhaust a first substrate to attract and hold the first substrate on a bottom surface thereof; a second holder disposed under the first holder, and configured to vacuum-exhaust a second substrate to attract and hold the second substrate on a top surface thereof; a mover configured to move the first holder and the second holder relatively in a horizontal direction; a laser interferometer system configured to measure a position of the first holder or the second holder which is moved by the mover; a linear scale configured to measure a position of the mover; and a controller configured to control the mover based on a measurement result of the laser interferometer system and a measurement result of the liner scale.

An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.

A semiconductor device includes: an insulated circuit substrate including a base plate, a resin layer on the base plate, and a circuit pattern on the resin layer; a semiconductor chip that is rectangular and is bonded to the circuit pattern such that a side edge of the semiconductor chip is spaced inwardly from an outer peripheral edge of the circuit pattern by a predetermined distance; a case on the resin layer and surrounds the circuit pattern and the semiconductor chip; and a sealing material that covers the insulated circuit substrate and semiconductor chip and is surrounded by the case. The predetermined distance and thickness of the circuit pattern are greater than or equal to 0.1 of a length of one side of the semiconductor chip. A peripheral region of the case and a peripheral region of the resin layer are connected to each other via an adhesive layer.

Provided herein include various examples of an apparatus, a sensor system and examples of a method for manufacturing aspects of an apparatus, a sensor system. The method may include forming bumps on a surface of one or more electrical contacts, where the one or more electrical contacts are accessible on an upper surface of a die, where the die is oriented on a substrate, and where the electrical contacts comprise bonding pads. The method may also include coupling one or more additional electrical contacts to the one or more electrical contacts, where the coupling comprises wire-bonding each additional electrical contact of the additional electrical contacts to one of the one or more electrical contacts accessible on the upper surface of the die, via a portion of the bumps on the surface of the one or more electrical contacts, thereby forming wire-bonded connections.

In one example, an electronic device comprises a substrate structure, comprising a base comprising a top side and a bottom side, a first lead, and a flag comprising a top side, a bottom side, and a flag lead. The electronic device also comprises an electronic component comprising a top side and a bottom side, a first electrode at the bottom side of the electronic component, and second electrode at the top side of the electronic component, an encapsulant contacting a lateral side of the electronic component and a lateral side of the base, and a first interconnect in the encapsulant, coupled between the first electrode and the first lead. The second electrode is coupled with the flag lead via the base. Other examples and related methods are also disclosed herein.

A semiconductor component has a circuit carrier with a first conductor layer, in which a first conductor path is formed. A first thyristor chip has, on its upper face, an anode contact and a gate contact and, on its lower face, a cathode contact placed for electrical connection on the first conductor path. A second thyristor chip has, on its upper face, a cathode contact and a gate contact and, on its lower face, an anode contact placed for electrical connection on the first conductor path. At least one electrically conductive connection element connects the anode contact of the first thyristor chip to the cathode contact of the second thyristor chip. The first conductor path thus establishes an electrical connection between the cathode contact of the first thyristor chip and the anode contact of the second thyristor chip.

The invention relates to a substrate arrangement, to a method for producing an electronic assembly and to an electronic assembly. The substrate arrangement comprises (a) a metal foil comprising an upper side and an underside, (b) a silver layer arranged on the underside of the metal foil, and (c) a silver sinter layer arranged on the silver layer, wherein the silver layer has a thickness d(Ag) in the range of 20-1500 nm.

A package substrate includes at least one insulating layer, upper circuit wirings having a plurality of pad patterns that extend on the at least one insulating layer, and a plurality of plating patterns respectively on the plurality of pad patterns. Each of the pad patterns has a geometric characteristic of surface waviness. Each of the plating patterns covers a surface of each of the pad patterns and has a geometric characteristic of predetermined surface roughness.