A described example includes: a semiconductor die having a device side surface and an opposing backside surface, the backside surface mounted to a die pad of a lead frame, the lead frame comprising conductive leads spaced from the die pad; a conductor layer overlying the device side surface; bond pads including bond pad conductors formed in the conductor layer, a nickel layer over the bond pad conductors, and a palladium or gold layer over the nickel layer; conductor traces formed in the conductor layer, the conductor traces free from the nickel layer and the palladium or gold layer; bond wires bonded to the bond pads electrically coupling the bond pads to conductive leads; and mold compound covering the semiconductor die, the bond pads, the bond wires, and portions of the lead frame, wherein portions of the conductive leads are exposed from the mold compound to form terminals.

An electronic device includes a multilevel ceramic body, first, second, and third plates, and first and second semiconductor dies, with the multilevel ceramic body having opposite first and second sides, a first and second openings in the first side, a third opening in the second side, and a ceramic separator structure defining first and second interior portions between the first and second openings. The first plate is attached to the first side and covers the first opening, the second plate is attached to the first side and covers the second opening, the third plate is attached to the second side and covers the third opening, the first semiconductor die is in the first interior portion, and the second semiconductor die is in the second interior portion of the ceramic body.

An integrated circuit (IC) device comprises a package substrate with traces configured to electrically connect with a plurality of IC device connection mechanisms. An IC die is mounted on the package substrate. The IC die includes pads. Wires electrically connect the pads of the IC die to the traces of the package substrate, including a first wire that electrically connects a first pad of the IC die to the first trace of the package substrate. A first metallic structure of the package substrate is electrically connected to the first trace and is configured to mitigate adverse effects of an inductance of the first wire.

In a semiconductor device, a first structure including a first uneven unit and a second structure covering the first structure and including a second uneven unit are formed in a bonding region defined in a semiconductor substrate. Metal wiring is joined to the second uneven unit in the second structure. A depth of a recess in the second uneven unit is shallower than a depth of a recess in the first uneven unit. An insulating member defining the bonding region is formed so as to reach the semiconductor substrate.

A wedge bonding tool is provided. The wedge bonding tool includes a body portion including a tip portion, the tip portion terminating at a working end of the wedge bonding tool. The tip portion includes (i) two opposing walls, and (ii) an adjoining surface between the two opposing walls. The adjoining surface includes a flat area. The two opposing walls and the flat area define a groove configured to receive a wire. The flat area has a width of at least 20% of a width of the groove at the working end.

A semiconductor device includes a mounting substrate having a first surface, a semiconductor chip mounted on the first surface and having a second surface facing a side opposite to the first surface, and a wire extending from a first joint point on the first surface toward a second joint point on the second surface and electrically connecting the mounting substrate and the semiconductor chip to each other by connecting the first joint point and the second joint point to each other. The wire includes a first part, a first bent portion, a second part, a second bent portion, and a third part arranged in order from the first joint point toward the second joint point. The first part is positioned on the first surface side with respect to the second surface when viewed in a first direction along the first surface and the second surface.

Semiconductor device includes: semiconductor elements electrically connected in parallel; pad portion electrically connected to the semiconductor elements; and terminal portion electrically connected to the pad portion. As viewed in thickness direction, the semiconductor elements are aligned along first direction perpendicular to the thickness direction. The pad portion includes closed region surrounded by three line segments each formed by connecting two of first, second and third vertex not disposed on the same straight line. As viewed in thickness direction, the first vertex overlaps with one semiconductor element located in outermost position in first sense of the first direction. As viewed in the thickness direction, the second vertex overlaps with one semiconductor element located in outermost position in second sense of the first direction. As viewed in the thickness direction, the third vertex is located on perpendicular bisector of the line segment connecting the first and second vertex.

A semiconductor package includes a metallic substrate, the metallic substrate including a roughened surface, a semiconductor die including bond pads, and an adhesive between the roughened surface of a topside of the metallic substrate and the semiconductor die, therein bonding the semiconductor die to the metallic substrate. The adhesive includes a resin. The metallic substrate further includes a groove about a perimeter of the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic substrate. The groove straddles the topside and a sidewall of the metallic substrate.

A memory system package structure and a manufacturing method thereof are disclosed. For example, the memory system package structure can include a memory chip, a memory controller and a distribution layer. The memory chip can include a first surface. The memory controller can be positioned on the first surface. The redistribution layer can be positioned on a side of the memory controller facing away from the memory chip. The memory chip and the memory controller can be electrically connected with the redistribution layer.

A semiconductor package includes a semiconductor die; a die pad having a first surface coupled to the semiconductor die and a second surface opposite the first surface, the die pad including an extension that comprises a first V-shaped groove in the second surface; a first conductive terminal having first and second ends and a third surface facing a same direction as the second surface, the third surface comprising a second V-shaped groove; a second conductive terminal having third and fourth ends and a fourth surface facing the same direction as the second surface, the fourth surface comprising a third V-shaped groove, the extension in between the second and fourth ends; and a mold compound covering the die, the die pad, and the first and second conductive terminals, the mold compound filling the first, second, and third V-shaped grooves, and the first and third ends extending to an exterior of the mold compound.