In one example, an electronic device, comprises a substrate comprising a dielectric structure and a conductive structure, an electronic component over a top side of the substrate, wherein the electronic component is coupled with the conductive structure; an encapsulant over the top side of the substrate and contacting a lateral side of the electronic component, wherein the encapsulant comprises a first trench on a top side of the encapsulant adjacent to the electronic component, a lid over the top side of the encapsulant and covering the electronic component; and an interface material between the top side of the encapsulant and the lid, and in the first trench. Other examples and related methods are also disclosed herein.

A semiconductor device of embodiments includes: a die pad; a semiconductor chip fixed on the die pad; and a sealing resin covering the semiconductor chip and at least a part of the die pad. The sealing resin has a first protruding portion provided on one side surface and a second protruding portion provided on another side surface. The cross-sectional area of the first protruding portion is equal to or more than 10% of the maximum cross-sectional area of the sealing resin. The cross-sectional area of the second protruding portion is equal to or more than 10%; of the maximum cross-sectional area. The maximum cross-sectional area is equal to or more than 6 mm.sup.2.

A bonded structure is disclosed. The bonded structure can include an interconnect structure. The bonded structure can also include a first die directly bonded to the interconnect structure. The bonded structure can also include a second die mounted to the interconnect structure. The second die is spaced apart from the first die laterally along an upper surface of the interconnect structure. The second die is electrically connected with the first die at least partially through the interconnect structure. The bonded structure can further include a dielectric layer that is disposed over the upper surface of the interconnect structure between the first die and the second die.

As an example of a semiconductor device is disclosed. The semiconductor device 1 includes a semiconductor die 3 and a wiring layer 5a to which the semiconductor die 3 is attached. The semiconductor die 3 includes a semiconductor substrate 3a having a first surface and a second surface opposite thereto, a plurality of terminal electrodes 3b provided on the first surface of the semiconductor substrate 3a, and a cured resin layer 3c. The cured resin layer 3c is provided on the first surface of the semiconductor substrate 3a so as to cover the plurality of terminal electrodes 3c. The semiconductor die 3 can be, for example, a bride die that connects a semiconductor die 2a and a semiconductor die 2b to each other.

The present disclosure relates to a method for manufacturing electronic chips comprising, in order:

a. forming metal contacts on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits have been previously formed;

b. depositing a first protective resin on the metal contacts and the first face of the semiconductor substrate;

c. forming first trenches of a first width on the side of a second face of the semiconductor substrate;

d. depositing a second protective resin in the first trenches and on the second face of the semiconductor substrate;

e. forming second trenches of a second width, less than the first width, opposite the first trenches up to the metal contacts; and

f. forming third trenches opposite the second trenches, the third trenches extending through the metal contacts.

Bonded die structures and methods of fabricating bonded die structures including improved positioning of the dies used to form the structures. Improved positioning may be achieved by providing non-linear alignment features around the periphery of the dies that may facilitate accurate positioning of the dies with respect to one or more alignment marks on the target structures on which the dies are placed. The non-linear alignment features may include features formed in the peripheral edges of the dies, such as indent portions extending inwardly from the peripheral edges of the dies and/or outward bulge portions extending outwardly from the peripheral edges of the dies. Alternatively, or in addition, the non-linear alignment features may be features formed in a seal ring structure of the dies. The non-linear alignment features may improve the accuracy of the positioning of the dies relative to alignment mark(s) on the target structures using optical detection systems.

A method is provided, including forming a wafer structure including a sacrificial layer between first and second substrates; forming first sacrificial structures within the second substrate in the spacing regions; forming second sacrificial structure within the second substrate; forming conductive vias through the second substrate in the die regions; forming dielectric layers over the second substrate and forming conductive features in the dielectric layers in the die regions; forming first windows through the dielectric layers and extending to the first sacrificial structures; forming second window through the dielectric layers and extending to the second sacrificial structure; forming a protective layer over the dielectric layers and filling the first windows; attaching a carrier substrate to the protective layer; removing the sacrificial layer, first sacrificial structures, and second sacrificial structure by flowing an etchant through the at least one second window; removing the protective layer; and detaching the carrier substrate.

A method of manufacturing a semiconductor device packaging panel is provided. The method includes forming a packaging substrate having a plurality of grooves orthogonally arranged and substantially surrounding a plurality of package sites. A plurality of semiconductor die is affixed on a first major side of the packaging substrate. Each semiconductor die of the plurality of semiconductor die is affixed at a unique package site of the plurality of package sites. An encapsulant encapsulates the first major side of the packaging substrate such that each semiconductor die of the plurality of semiconductor die is encapsulated by the encapsulant. A singulation cut is formed along each groove of the plurality of grooves of the packaging substrate to form individual semiconductor device units.

Electronic packages, die structures and methods of fabrication are described in which a recess is formed by removing material from the edges and corners of a die that may increase the risk of non-bonding or delamination. In an embodiment, a die includes a recess with a width that extends from a perimeter edge to a recessed edge, and a depth that extends from a top surface to a recess floor. In some embodiments, the recess is filled with gap fill material. In other embodiments, the recess is not filled with gap fill material.

Implementations of a substrate may include a first set of tie bars; a second set of tie bars; and a plurality of leads coupled between the first set of tie bars and the second set of tie bars. The first set of tie bars may intersect with the second set of tie bars. Each intersection of the first set of tie bars and the second set of tie bars may be downset from the plurality of leads.