An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

A method includes bonding a first package component over a second package component. The second package component includes a plurality of dielectric layers, and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes dispensing a stress absorber on the second package component, curing the stress absorber, and forming an encapsulant on the second package component and the stress absorber.

In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.

A display includes a wiring pad and a dummy pad on a first substrate. A first planarization layer is disposed on the wiring pad and the dummy pad. A first pad electrode layer is connected to the wiring pad and a second pad electrode layer is connected to the dummy pad. The first and second pad electrode layers are disposed on the first planarization layer. A first insulating layer covers the first and second pad electrode layers. A first pad electrode upper layer is disposed on the first pad electrode layer. A second pad electrode upper layer is disposed on the second pad electrode layer. The wiring pad, the first pad electrode layer, and the first pad electrode upper layer are electrically connected. The dummy pad, the second pad electrode layer, and the second pad electrode upper layer are electrically connected.

A semiconductor package includes a support wiring structure, a semiconductor chip on the support wiring structure, a connection structure on the support wiring structure and spaced apart from the semiconductor chip in a horizontal direction, an interposer including a central portion and an outer portion and having a recess portion provided on a lower surface of the central portion facing the semiconductor chip, wherein the central portion is on the semiconductor chip and the connection structure is connected to the outer portion, and a metal plate disposed along a portion of a surface of the recess portion inside the interposer, wherein the metal plate extends along a side surface of the outer portion of the interposer and the lower surface of the central portion of the interposer, and the metal plate has a cavity passing through a vicinity of a center of the metal plate planarly.

A method for forming a package structure is provided. The method includes transporting a first package component into a processing chamber. The method includes positioning the first package component on a chuck table. The method includes using the chuck table to heat the first package component. The method includes holding a second package component with a bonding head. The bonding head communicates with a plurality of vacuum devices via a plurality of vacuum tubes, and the vacuum devices each operate independently. The method also includes bonding the first package component and the second package component in the processing chamber to form the package structure.

A chip packaging structure and a method for manufacturing are disclosed, including a semiconductor chip, a device layer, and a warpage compensation layer, which is bonded to the device layer. The warpage compensation layer has a thermal expansion coefficient matching that of the semiconductor chip, the mismatch in coefficients of thermal expansion between the substrate and the semiconductor chip can be compensated, thereby reducing or eliminating warpage. The thermal expansion coefficient of the warpage compensation layer is also close to that of the semiconductor chip, so they form a structure that has an in-between thermal expansion coefficient, which creates synchronous tensions or stress on top and bottom surfaces of the substrate to prevent it from bending toward one side.

A packaged electronic device comprises a power semiconductor die that includes a first terminal and a second terminal, a power substrate comprising a dielectric substrate having a first metal cladding layer on an upper surface thereof, an encapsulation covering the power semiconductor die and at least a portion of the power substrate, a first lead extending through the encapsulation that is electrically connected to the first terminal, and a second lead extending through the encapsulation that is electrically connected to the second terminal. The first terminal is bonded to the first lead via a first transient liquid phase solder joint.