A semiconductor package includes a metallic substrate, the metallic substrate including a roughened surface, a semiconductor die including bond pads, and an adhesive between the roughened surface of a topside of the metallic substrate and the semiconductor die, therein bonding the semiconductor die to the metallic substrate. The adhesive includes a resin. The metallic substrate further includes a groove about a perimeter of the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic substrate. The groove straddles the topside and a sidewall of the metallic substrate.

A die including a die body having a first body surface, a second body surface on an opposite side of the die body as the first body surface, an interconnect region adjacent to the first body surface including interconnect dielectric layers with metal lines and vias, a transistor region above the interconnect region, the metal lines and vias making electrical connections to one or more power rails of the transistor region and electrically connected to transistors of the transistor region, a power region above the transistor region including an electro-conductive film on the second body surface and TSVs in the power region, an outer end of the TSV contacting the film and an embedded end of the TSVs contacting one of the power rails. A method of manufacturing an IC package and computer with the IC package are also disclosed.

A package structure is provided. The package structure includes a substrate, a first electronic component, an encapsulant, and a protective element. The first electronic component is over the substrate. The encapsulant is over the substrate and defines a cavity that exposes the first electronic component. The protective element covers the first electronic component. A lateral surface of the protective element is substantially aligned with a lateral surface of the encapsulant.

A method comprises: covering at least part of the integrated circuit with a material, the material including an opening that penetrates through the material; and forming a layer of nanoparticles on at least part of an internal wall of the opening and over at least part of the integrated circuit.

Systems, methods, and devices related to techniques for repeating inter-die signals within a multi-die package of a memory device are disclosed. The multi-die package includes a memory stack including a first memory die handling interfacing with a host for the package and at least one second memory die coupled to and configured to communicate with the first memory die via an inter-die connection. A technique involves incorporating the use of a multiplexer positioned in front of the transmitter of each die to facilitate repetition of inter-die signals within the memory stack as needed depending on various factors associated with the memory stack, such as, but not limited to, the type of signal, the intended recipient of the inter-die signals, and the stack height of the memory stack.

A method includes providing an IC package having a lead and a die encapsulated in a mold compound. The mold compound extends from a top mold surface to a base mold surface of the IC package. The method also includes trenching the mold compound from the top mold surface to the lead to form a trench. The method further includes forming a vertical wettable flank by filling the trench with a conductive material.

A semiconductor device, a semiconductor package including such a semiconductor device and a method of manufacturing such a semiconductor package are presented. The semiconductor device includes a die and a leadframe. The semiconductor device further includes a wire-bond interconnect structure including one or more pairs of wires. Herein, a pair of wires includes two wires that are bonded together at one end at the die and that are bonded together on the other end at the leadframe.

Aspects of the subject disclosure may include, for example, system, comprising a substrate having an interconnect in or on a surface of the substrate, a riser disposed over the surface, the riser being configured with one or more through riser vias for coupling to the interconnect, a device positioned over the surface, the device having one or more conductive contacts residing in a plane of the device, and one or more wire bonds coupling the one or more through riser vias with the one or more conductive contacts thereby enabling connectivity of the interconnect to be raised toward or to the plane of the device such that at least one of the one or more wire bonds has a limited physical length. Other embodiments are disclosed.