In a copper alloy bonding wire for semiconductor devices, the bonding longevity of a ball bonded part under high-temperature and high-humidity environments is improved. The copper alloy bonding wire for semiconductor devices includes in total 0.03% by mass or more to 3% by mass or less of at least one or more kinds of elements selected from Ni, Zn, Ga, Ge, Rh, In, Ir, and Pt (first element), with the balance Cu and inevitable impurities. The inclusion of a predetermined amount of the first element suppresses production of an intermetallic compound susceptible to corrosion under high-temperature and high-humidity environments at the wire bonding interface and improves the bonding longevity of a ball bonded part.

A semiconductor device according to one aspect includes a pad portion, an insulating layer that supports the pad portion, a first wiring layer that is formed in a layer below the pad portion and extends in a first direction below the pad portion, and a conductive member that is joined to a front surface of the pad portion and extends in a direction forming an angle of 30 to 30 with respect to the first direction. A semiconductor device according to another aspect includes a pad portion, an insulating layer that supports the pad portion, a first wiring layer that is formed in a layer below the pad portion and extends in a first direction below the pad portion, and a conductive member that is joined to a front surface of the pad portion and has a joint portion that is long in one direction in plan view and an angle of a long direction of the joint portion with respect to the first direction is 30 to 30.

A semiconductor device having an improved bonding reliability of wire bonding is provided. The semiconductor device includes a semiconductor chip, a die pad, an inner lead, and a bonding wire. The semiconductor chip has a first lower surface, and a bonding pad provided on a first upper surface. The bonding pad has a second upper surface. The die pad has a third upper surface. The inner lead has a fourth upper surface. The semiconductor chip is mounted on the die pad such that the first lower surface faces the third upper surface. The bonding pad and the inner lead are electrically connected to each other via the bonding wire. In cross-sectional view, the second upper surface, to which the bonding wire is connected, of the bonding pad is located at the same height as the fourth upper surface, to which the bonding wire is connected, of the inner lead.

A semiconductor package includes: a package substrate including a first surface and a second surface opposite each other; at least one signal pad arranged in a first direction, at least one ground pad spaced apart from the at least one signal pad in a second direction; and a semiconductor chip on the package substrate, the semiconductor chip including at least one first pad and at least one second pad. The package substrate includes at least one signal line connected to the at least one signal pad; and a at least one ground line connected to the at least one ground pad, in which the at least one ground line extends between the at least one signal pad and the at least one ground pad in the first direction, and in which the at least one second pad is connected to the at least one ground pad through a second bonding wire.

Implementations of an image sensor package may include an image sensor die including at least one bond pad thereon; a bond wire wirebonded to the at least one bond pad; and an optically transmissive lid coupled to the image sensor die with an optically opaque film adhesive over the at least one bond pad. The bond wire may extend through the optically opaque film adhesive to the at least one bond pad.

A fan-out stacked semiconductor package structure and a packaging method thereof are disclosed. The structure includes a three-dimensional memory chip package unit and a two-dimensional fan-out peripheral circuit chip SiP package unit. The three-dimensional memory chip package unit includes: at least two memory chips laminated in a stepped configuration; a first rewiring layer; wire bonding structures, each of which being electrically connected to the bonding pad and the first rewiring layer; a first encapsulating layer; and first metal bumps, formed on the first rewiring layer. The two-dimensional fan-out peripheral circuit chip SiP package unit includes: a second rewiring layer; at least one peripheral circuit chip; a third rewiring layer, bonded to the peripheral circuit chip; metal connection pillars; a second encapsulating layer, encapsulating the peripheral circuit chip and the metal connection pillars; and second metal bumps, formed on the second rewiring layer. The first metal bumps are bonded to the third rewiring layer.

The semiconductor module includes a first device that has an IGBT and a second device that has a reflux diode which is anti-parallel connected to the IGBT, which has a forward threshold voltage less than a reverse withstand voltage of the IGBT, and which has a forward breakdown voltage in excess of the reverse withstand voltage of the IGBT.

A semiconductor package includes a package substrate, a plurality of first semiconductor chips stacked on an upper surface of the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip at a first height from the upper surface of the package substrate, the uppermost semiconductor chip including a free end portion. Conductive wires respectively electrically connect chip pads of the first semiconductor chips to substrate pads of the package substrate. A plurality of first support structures each have a first end attached to the upper surface of the package substrate and an opposite second end attached to the free end portion of the uppermost semiconductor chip. The first support structures are inclined at an angle relative to the package substrate.