A power package includes at least one power substrate having at least one power trace, at least one power device on the at least one power trace, signal terminals, and at least one signal connection assembly. The at least one signal connection assembly includes at least one of the following: at least one signal trace that is thinner than the at least one power trace; at least one embedded routing layer within the at least one power substrate; and/or at least one routing layer on the at least one power substrate.

A semiconductor package includes a substrate, a first semiconductor die disposed on the substrate, a second semiconductor die stacked on the first die and offset from it in a first direction and a second direction that are perpendicular to each other, and a third semiconductor die stacked on the first and second dies and offset from them in the first direction. The first semiconductor die includes a first pad and a second pad, arranged successively in the second direction. The second semiconductor die includes a third pad and a fourth pad, and the third semiconductor die includes a fifth pad and a sixth pad, each arranged successively in the second direction. A first conductive pattern connects the first and fifth pads, while a second conductive pattern connects the second, fourth, and sixth pads. The first and second conductive patterns are spaced apart from the third pad.

Power semiconductor device packages and methods for manufacturing the same are provided. In one example, a power semiconductor device package may include a housing, a submount, and a conjoined semiconductor die structure on the submount. The conjoined semiconductor die structure may include at least two semiconductor die having a common substrate. The conjoined semiconductor die structure may be cut from a semiconductor wafer and may be packaged based on die viability data indicative of an operability of each respective semiconductor die of the at least two semiconductor die.

A device may include a first chip and a second chip, the first chip and the second chip being connected by a set of wirebonds. The device may include a ground cover structure providing a ground over the set of wirebonds. The ground cover structure may include a dielectric structure having a cavity on a first side of the dielectric structure. The ground cover structure may include a metal structure on a second side of the dielectric structure. The ground cover structure may include a dielectric material within the cavity of the dielectric structure.

Within the cavity, each wirebond in the set of wirebonds may be encapsulated by the dielectric material or by a combination of the dielectric material and the dielectric structure.

A semiconductor module, including a first main wiring line connecting portion and a second main wiring line connecting portion, and a main output wiring line connecting portion is provided. The circuit board includes a circuit region in which the first circuit and the second circuit are arranged alongside each other in the first direction, and a first connecting region and a second connecting region arranged sandwiching the circuit region in a second direction orthogonal to the first direction. The first main wiring line connecting portion and the second main wiring line connecting portion are provided in the first connecting region, and the main output wiring line connecting portion is provided in the second connecting region.

A semiconductor package according to an embodiment of the present disclosure includes: a substrate; a semiconductor chip on the substrate and electrically connected to the substrate; at least one heat dissipation wire connected to the semiconductor chip; and an encapsulant on at least a portion of each of the semiconductor chip and the heat dissipation wire. The heat dissipation wire is exposed to one side surface of side surfaces of the encapsulant.

A chip package structure includes a conductive substrate, a chip, a gate connecting part, a source connecting part, a drain connecting part, a gate conductive wire, a source conductive wire, and a plurality of pins. The gate connecting part is located at a side of the chip. The source connecting part is located at the side of the chip and is separated from the gate connecting part. The source conductive wire is connected to a source electrode of the chip and the source connecting part. The pins include a first pin, a second pin, and one or more third pins. The first pin is connected to the gate connecting part. The second pin is connected to the one or more third pins by the source connecting part.

An electronic package is provided, in which an electronic element is arranged on a carrier structure having a plurality of wire-bonding pads arranged on a surface of the carrier structure, and a plurality of bonding wires are connected to a plurality of electrode pads of the electronic element and the plurality of wire-bonding pads. Further, among any three adjacent ones of the plurality of wire-bonding pads, a long-distanced first wire-bonding pad, a middle-distanced second wire-bonding pad and a short-distanced third wire-bonding pad are defined according to their distances from the electronic element. Therefore, even if the bonding wires on the first to third wire-bonding pads are impacted by an adhesive where a wire sweep phenomenon occurred when the flowing adhesive of a packaging layer covers the electronic element and the bonding wires, the bonding wires still would not contact each other, thereby avoiding short circuit problems.

A method of determining a sequence for creating a plurality of wire loops is provided. The method includes (a) providing workpiece data for a workpiece. The workpiece data includes (i) position data for bonding locations of the workpiece, and (ii) wire loop data for a plurality of wire loops providing interconnection between ones of the bonding locations. The method also includes (b) analyzing the workpiece data. The step of analyzing includes considering overlap conditions between ones of the plurality of wire loops, considering wire loop heights of ones of the plurality of wire loops, considering lateral bend conditions between ones of the plurality of wire loops, and considering wire loop positions for ones of the plurality of wire loops. The method also includes (c) providing a sequence of creating the plurality of wire loops in connection with the workpiece at least partially based on the results of step (b).

A semiconductor package includes a substrate including a wiring; a chip stack including a plurality of semiconductor chips stacked on the substrate, wherein each of the plurality of semiconductor chips has upper and lower surfaces, opposite to each other, front and rear surfaces, opposite to each other, left and right surfaces, opposite to each other, and connection pads disposed on the upper surface adjacent to the front surface; bonding wires electrically connecting the connection pads to the wiring of the substrate; a plurality of attachment films disposed on the lower surface of each of the plurality of semiconductor chips; a mold layer covering the chip stack and the bonding wires; and connection bumps disposed below the substrate, and electrically connected to the wiring, wherein at least one of the plurality of attachment films covers the rear surface of at least one semiconductor chip among the plurality of semiconductor chips.