In a described example, an apparatus includes: a metal leadframe including a dielectric die support formed in a central portion of the leadframe, and having metal leads extending from the central portion, portions of the metal leads extending into the central portion contacted by the dielectric die support; die attach material over the dielectric die support; a semiconductor die mounted to the dielectric die support by the die attach material, the semiconductor die having bond pads on a device side surface facing away from the dielectric die support; electrical connections extending from the bond pads to metal leads of the leadframe; and mold compound covering the semiconductor die, the electrical connections, the dielectric die support, and portions of the metal leads, the mold compound forming a package body.

Semiconductor device includes: semiconductor elements electrically connected in parallel; pad portion electrically connected to the semiconductor elements; and terminal portion electrically connected to the pad portion. As viewed in thickness direction, the semiconductor elements are aligned along first direction perpendicular to the thickness direction. The pad portion includes closed region surrounded by three line segments each formed by connecting two of first, second and third vertex not disposed on the same straight line. As viewed in thickness direction, the first vertex overlaps with one semiconductor element located in outermost position in first sense of the first direction. As viewed in the thickness direction, the second vertex overlaps with one semiconductor element located in outermost position in second sense of the first direction. As viewed in the thickness direction, the third vertex is located on perpendicular bisector of the line segment connecting the first and second vertex.

The package-on-package (POP) structure includes a first package unit of three-dimensional fan-out memory chips and a SiP package unit of the two-dimensional fan-out peripheral circuit chip. The first package unit includes: memory chips laminated in a stepped configuration; a molded substrate; wire bonding structures; a first rewiring layer; a first encapsulating layer; and first metal bumps, formed on the first rewiring layer. The SiP package unit includes: a second rewiring layer; a peripheral circuit chip; a third rewiring layer, bonded to the circuit chip; first metal connection pillars; a second encapsulating layer for the circuit chip and the first metal connection pillars; and second metal bumps on the second rewiring layer. The first metal bumps are bonded to the third rewiring layer. Integrating the two package units into the POP is enabled by three rewiring layers and the molded substrate which supports the first package unit during wire bonding process.

A method of manufacturing a semiconductor device is provided. The method includes forming a package leadframe including a die pad, a first ridge formed at a first outer edge of the die pad, a second ridge formed at a second outer edge of the die pad opposite of the first outer edge and separate from the first ridge, and a plurality of leads surrounding the die pad. A semiconductor die is attached to the die pad by way of a die attach material. The semiconductor die is located on the die pad between the first ridge and the second ridge. An encapsulant encapsulates the semiconductor die and at least a portion of the package leadframe.

A semiconductor device of an embodiment includes: a first semiconductor element; a first insulating resin that seals the first semiconductor element; a wiring substrate having a pad; a first wiring that extends from the first semiconductor element toward the wiring substrate, and has a first head portion and a first column portion, the first column portion connected to the first semiconductor element and the first head portion exposed on a surface of the first insulating resin; and a first conductive bonding agent that electrically connects the first head portion of the first wiring and the pad. When a surface of the first head portion facing a side of the first insulating resin is defined as a first surface. A surface of the first insulating resin on a side of the wiring substrate is defined as a second surface. A distance from a surface of the wiring substrate on a side of the first insulating resin to the first surface is defined as a first distance, and a distance from a surface of the wiring substrate on the side of the first insulating resin to the second surface is defined as a second distance. The first distance is shorter than the second distance.

Implementations of an image sensor package may include an image sensor die including at least one bond pad thereon; a bond wire wirebonded to the at least one bond pad; and an optically transmissive lid coupled to the image sensor die with an optically opaque film adhesive over the at least one bond pad. The bond wire may extend through the optically opaque film adhesive to the at least one bond pad.

A semiconductor device includes a plurality of semiconductor elements, each of which has a first electrode, a second electrode, and a third electrode, and is subjected to an ON-OFF control between the first electrode and the second electrode in accordance with a driving signal input to the third electrode. Further, the semiconductor device includes a control terminal to which the driving signal is input, a first wiring portion to which the control terminal is connected, a second wiring portion separated from the first wiring portion, a first connection member to conduct the first wiring portion and the second wiring portion, and a second connection member to conduct the second wiring portion and the third electrode of one of the plurality of semiconductor elements. The respective first electrodes of the plurality of semiconductor elements are electrically connected to one another, and respective second electrodes of the plurality of semiconductor elements are electrically connected to one another.

A semiconductor device includes a semiconductor die having a die surface, in which the die surface includes a bond pad. A ball bond has a distal surface and flattened-disk shape extending from the distal surface and terminating in a proximal surface spaced apart from the distal surface. The distal surface is coupled to the bond pad and a channel extends a depth into the proximal surface surrounding a central portion of the proximal surface. A bond wire extending from the central portion of the proximal surface, in which the channel is spaced apart from and surrounds the bond wire.

A semiconductor package may include a package substrate; first semiconductor chips sequentially stacked on an upper surface of the package substrate; a second semiconductor chip on an uppermost first semiconductor chip among the first semiconductor chips, the second semiconductor chip having an overhang region protruding from one side of the uppermost first semiconductor chip and an overlapping region overlapping the uppermost first semiconductor chip, the second chip pads including first bonding pads in the overhang region and second bonding pads in the overlapping region; first conductive bumps respectively on the first bonding pads; second conductive bumps respectively on the second bonding pads; vertical wires extending from the first conductive bumps to substrate pads of the package substrate, respectively; and a molding member covering the first semiconductor chips, the second semiconductor chip, and the vertical wires.

A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.