In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

Provided are a semiconductor structure and a method of forming the same. The semiconductor structure includes: a substrate, an under bump metallurgy (UBM) structure, and a solder. The UBM structure is disposed over the substrate. The UBM structure includes a first metal layer; a second metal layer disposed on the first metal layer; and a third metal layer disposed on the second metal layer. A sidewall of the first metal layer is substantially aligned with a sidewall of the second metal layer, and a sidewall of the third metal layer is laterally offset inwardly from the sidewalls of the first and second metal layers. The solder is disposed on the third metal layer.

A microelectronic device includes a first microelectronic device structure, a second microelectronic device structure bonded to the first microelectronic device structure, and cruciform contact structures at a bonding interface of the first microelectronic device structure and the second microelectronic device structure. The cruciform contact structures respectively include a first conductive bar and a second conductive bar bonded to the first conductive bar. The first conductive bar has a first rectangular shape, a major horizontal dimension of the first conductive bar oriented in a first direction. The second conductive bar has a second rectangular shape, a major horizontal dimension of the second conductive bar oriented in a second direction orthogonal to the first direction. Related methods and electronic systems are also described.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. A semiconductor structure includes a first chip. The first chip includes a first interconnect layer, a first conductive layer disposed on the first interconnect layer, a first dielectric layer covering the first conductive layer, and a first bonding pad embedded in the first dielectric layer and extending into the first conductive layer. The method of manufacturing the semiconductor structure includes the following operations. A first conductive layer is formed on a first interconnect layer. A first dielectric layer is formed on the first conductive layer and the first interconnect layer. The first dielectric layer is etched to form a first trench on the first conductive layer. A portion of the first conductive layer is etched to form a second trench. A first bonding pad is formed in the second trench.

Methods, systems, and devices for polymer material gap-fill for hybrid bonding in a stacked semiconductor system are described. A stacked semiconductor may include a first semiconductor die on a semiconductor wafer. A polymer material may be on the semiconductor wafer and may at least partially surround the first semiconductor die. A silicon nitride material may be on the first semiconductor die and on the polymer material. And a second semiconductor die may be hybrid bonded with a bonding material on the silicon nitride material.

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

Provided herein include various examples of an apparatus, a sensor system and examples of a method for manufacturing aspects of an apparatus, a sensor system. The method may include forming bumps on a surface of one or more electrical contacts, where the one or more electrical contacts are accessible on an upper surface of a die, where the die is oriented on a substrate, and where the electrical contacts comprise bonding pads. The method may also include coupling one or more additional electrical contacts to the one or more electrical contacts, where the coupling comprises wire-bonding each additional electrical contact of the additional electrical contacts to one of the one or more electrical contacts accessible on the upper surface of the die, via a portion of the bumps on the surface of the one or more electrical contacts, thereby forming wire-bonded connections.

A display device includes a display panel including a display area and a pad area. The display panel includes a base substrate, a pixel, a pad group, an alignment mark, and a protective layer. The pad group includes a plurality of pads arranged in a first direction. The alignment mark is spaced apart from the pad group in the first direction. The protective layer covers the pads and the alignment mark and a plurality of openings respectively exposing upper surfaces of the pads is defined in the protective layer. Each of the pads includes at least one pad pattern, and the alignment mark is disposed in a same layer as a pad pattern spaced farthest from the base substrate among the at least one pad pattern.

The invention provides improved techniques for bonding devices using copper-to-copper or other types of bonds. A substrate is cleaned to remove surface oxides and contaminants and then rinsed. The rinsed substrate is provided to coating unit where a protective coating is applied to the substrate. The protective coating may be applied by immersing the substrate in a bath or via chemical vapor deposition. In an aspect, the protective coating may be copper selective so that the protective coating is only applied to copper features of the substrate. The protective coating minimizes formation of oxides and other bond weakening forces that may form during bonding processes, such as bonding a copper wire to a copper bond pad of the substrate. In an aspect, an annealing process is used to cure the protective coating and remove small imperfections and other abnormalities in the protective coating prior to the bonding process.

An image sensor is provided. The image sensor includes a first semiconductor structure with photodiodes provided in a first semiconductor substrate, a first interconnection structure below the first semiconductor substrate, first bonding structures below the first interconnection structure and connected to the first interconnection structure, first shielding structures between the first bonding structures, and a first bonding insulating film surrounding lower regions of the first bonding structures and lower regions of the first shielding structures; and a second semiconductor structure a second interconnection structure provided in a second semiconductor substrate, second bonding structures contacting the first bonding structures on the second interconnection structure and connected to the second interconnection structure, second shielding structures between the second bonding structures and contacting the first shielding structures, and a second bonding insulating film surrounding upper regions of the second bonding structures and upper regions of the second shielding structures.