A gate electrode is formed in a trench. An insulating film is formed on the gate electrode so as to protrude from an upper surface of a semiconductor substrate. A sidewall spacer is formed on a side surface of the insulating film and on the upper surface of the semiconductor substrate. A hole is formed in a portion of the semiconductor substrate exposed from the insulating film and the sidewall spacer. A barrier metal film is formed in the hole. A second opening width of the hole at a second position, corresponding to a position of a junction surface between a body region and a source region, is larger than a first opening width of the hole at a first position, corresponding to a position of the upper surface of the semiconductor substrate. The barrier metal film includes a silicide film and a metal film.

The present application discloses a method for manufacturing an integrated structure of a metal-gate MOS transistor. Through a dry etching process, a medium-voltage device silicon recess is formed, and through a thermal oxidation process, a sacrificial oxide layer is formed on a bottom of the medium-voltage device silicon recess, thereby consuming silicon damaged by dry etching in the medium-voltage device silicon recess. Then, through a wet etch process, a hard mask layer, pad oxide layers in a low-voltage and a high-voltage region, and the sacrificial oxide layer in a medium-voltage region are removed. A thick oxide layer is then grown as a gate oxide layer of a medium-voltage device. The manufacturing method in the present application is fully compatible with existing processes and can reduce an effect of induced drain leakage without adding additional masks, thereby achieving an objective of reducing static power consumption of a metal-gate medium-voltage device.