A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO.sub.2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.

An insulated gate semiconductor device includes: a carrier transport layer of a first conductivity-type; an injection control region of a second conductivity-type; a carrier supply region of the first conductivity-type; a base contact region of the second conductivity-type; trenches penetrating the injection control region to reach the carrier transport layer; an insulated gate structure provided inside the respective trenches; an upper buried region of the second conductivity-type being in contact with a bottom surface of the injection control region; a lower buried region of the second conductivity-type being in contact with a bottom surface of the upper buried region and a bottom surface of the respective trenches; and a high-concentration region of the first conductivity-type provided inside the carrier transport layer to be in contact with a part of a bottom surface of the lower buried region.

A semiconductor device and a method of manufacturing the same capable of ensuring a sufficient breakdown voltage near a terminal end portion of a cell portion are provided. The cell portion includes a first cell column region and a second cell column region adjacent to each other, and a first cell trench gate and a second cell trench gate arranged between the first cell column region and the second cell column region. An outer peripheral portion includes an outer peripheral trench gate connected to an end portion of each of the first cell trench gate and the second cell trench gate, and a first outer peripheral column region arranged on the cell portion side with respect to the outer peripheral trench gate and extended across the first cell trench gate and the second cell trench gate in plan view.

A semiconductor device includes a semiconductor layer having a first face with a trench formed thereon and a second face opposite to the first face, a gate electrode, and a gate insulating layer. The semiconductor layer includes a first n-type semiconductor layer, a second n-type semiconductor layer, a p-type semiconductor layer, and an n-type semiconductor region. The trench is formed to penetrate through the p-type semiconductor layer and to reach the second n-type semiconductor layer. The p-type semiconductor layer includes an extended portion extending to a position closer to the second face of the semiconductor layer than the trench is. Such structure allows suppressing dielectric breakdown in the gate insulating layer.

The present invention involves a power device and a manufacturing method thereof. The method comprising steps of providing a semiconductor substrate, growing an epitaxial layer on the semiconductor substrate, forming an insulating layer on the epitaxial layer, forming a metal mask layer on the insulating layer, and performing an ion implantation process from above the metal mask layer on the epitaxial layer. The metal mask layer includes an ion implantation blocking region and an ion implantation penetration region.

A circular LDMOS device includes a lower drift layer disposed on a substrate, a drain region disposed on the lower drift layer, a source region having a circular ring shape surrounding the drain region and spaced apart from the drain region, a field insulating layer disposed between the drain region and the source region, and an upper drift layer disposed between the lower drift layer and the field insulating layer and having a conductivity type different from that of the lower drift layer.

A field-effect transistor includes: a semiconductor substrate having trenches; and a gate electrode disposed in the trenches. Breakdown voltage regions are provided in each inter-trench range. The breakdown voltage regions are arranged to form rows extending in a first direction intersecting the trenches. The rows are arranged at interval in a second direction parallel to the trenches. Each of the breakdown voltage regions extends from an upper side of a lower end of each of the trenches to a lower side of the lower end of each of the trenches, and is disposed at a distance from a gate insulating film. A drift region is in contact with the gate insulating film at a position between the breakdown voltage region and the gate insulating film.

An SGT MOSFET device and a manufacturing method of contact holes of the SGT MOSFET device relate to a field of power semiconductor device manufacturing. The manufacturing method includes steps of preparing a gate trench, source trenches, a shielding gate trench, and a pre-embedded ESD trench, preparing a cell structure, preparing an ESD region, a body region, and a source region by ion implantation and preparing a gate contact hole, a source contact hole, a shield gate contact hole, and ESD contact holes. By pre-embedding an ESD structure, depth differences between the gate contact hole, the source contact hole, the shielding gate contact hole, and the ESD contact holes are reduced, and the contact holes are prepared by only one photolithography process. The manufacturing method reduces one photolithography process and one process of growing ESD polysilicon, saves cost, and reduces difficulty of the manufacturing process.

An SGT MOSFET device and a manufacturing method of contact holes of the SGT MOSFET device relate to a field of power semiconductor device manufacturing. The manufacturing method includes steps of preparing a gate trench, source trenches, a shielding gate trench, and a pre-embedded ESD trench, preparing a cell structure, preparing an ESD region, a body region, and a source region by ion implantation and preparing a gate contact hole, a source contact hole, a shield gate contact hole, and ESD contact holes. By pre-embedding an ESD structure, depth differences between the gate contact hole, the source contact hole, the shielding gate contact hole, and the ESD contact holes are reduced, and the contact holes are prepared by only one photolithography process. The manufacturing method reduces one photolithography process and one process of growing ESD polysilicon, saves cost, and reduces difficulty of the manufacturing process.