An integrated circuit is fabricated by forming transistors having gates of orthogonal orientations and implanting, at two first rotations, a first pocket implant using a first dopant type with a masking pattern on a substrate surface layer, the two first rotations respectively forming two first pocket implantation angles and two first pocket implantation beam orientations, and implanting, at two second rotations, a retrograde gate-edge diode leakage (GDL) reduction pocket implant using a second dopant type with the masking pattern on the substrate surface layer, the two second rotations respectively forming two GDL-reduction implantation angles and two GDL-reduction implantation beam orientations. Owing to the different symmetries in implantation angles seen by the two orientations of transistors, leakage is reduced for transistors of both orientations and mismatch is maintained for transistors of one of the orientations, making these transistors suitable for use in analog circuits requiring matched pairs of transistors.

A method of manufacturing a semiconductor device according to an embodiment includes: forming a mask material having an opening on a surface of a silicon carbide layer; forming a trench in the silicon carbide layer using the mask material as a mask; performing first ion implantation for implanting carbon (C) into a bottom face of the trench using the mask material as a mask; forming a sidewall material on a side face of the trench; performing second ion implantation for implanting a p-type first impurity into the bottom face of the trench using the sidewall material as a mask; and performing heat treatment at 1600 C. or more.

A method of producing a power semiconductor device includes: providing a semiconductor body with a front side having a substantially horizontal area above both an active region and an edge termination region of the semiconductor body; forming, at the front side, a first insulation layer above both the active region and the edge termination region; forming, at the first insulation layer, a first mask layer that covers the edge termination region at least partially and exposes the active region; removing a portion of the first insulation layer covering the active region; and while the first mask layer or a modified first mask layer or another mask layer covers the edge termination region, subjecting the edge termination region to a first implantation processing step to form, in the edge termination region, one or more doped semiconductor regions.

A method of a semiconductor-on-insulator structure includes the following steps. A semiconductor donor substrate is provided. A first implantation process is performed to form an exfoliation layer of the semiconductor donor substrate with a first ion concentration. A second implantation process is performed on a perimeter region of the exfoliation layer to form a high concentration region of the exfoliation layer with a second ion concentration higher than the first ion concentration. The semiconductor donor substrate is bonded to a semiconductor handle substrate, so that the exfoliation layer with the high concentration region is bonded to the semiconductor handle substrate. An annealing process is performed to separate the exfoliation layer from the rest of the semiconductor donor substrate.

A method of a semiconductor-on-insulator structure includes the following steps. A semiconductor donor substrate is provided. A first implantation process is performed to form an exfoliation layer of the semiconductor donor substrate with a first ion concentration. A second implantation process is performed on a perimeter region of the exfoliation layer to form a high concentration region of the exfoliation layer with a second ion concentration higher than the first ion concentration. The semiconductor donor substrate is bonded to a semiconductor handle substrate, so that the exfoliation layer with the high concentration region is bonded to the semiconductor handle substrate. An annealing process is performed to separate the exfoliation layer from the rest of the semiconductor donor substrate.

A method for manufacturing a semiconductor device, and a semiconductor device. The method includes: providing a semiconductor substrate of a first conductivity type, forming a deep well of a second conductivity type in the semiconductor substrate, forming a channel region of the first conductivity type, a first well region of the first conductivity type, and a drift region of the second conductivity type in the deep well, the first well region and the channel region being spaced by a portion of the deep well, the drift region being located between the channel region and the first well region, forming an ion implantation region of the first conductivity type in the deep well, the ion implantation region being located under the drift region, and forming a source region of the second conductivity type and a drain region of the second conductivity type in the deep well.

Some embodiments of the present disclosure provide a method of forming a semiconductor device including forming a dielectric layer stack on an epitaxial layer. The dielectric layer stack includes at least one first layer and at least one second layer, the at least one first layer is made of a first material, the at least second layer is made of a second material different from the first material. The dielectric layer stack is patterned to form a staircase-shaped dielectric layer stack. An ion implantation process is performed to the epitaxial layer by using the staircase-shaped dielectric layer stack.

Some embodiments of the present disclosure provide a method of forming a semiconductor device including forming a dielectric layer stack on an epitaxial layer. The dielectric layer stack includes at least one first layer and at least one second layer, the at least one first layer is made of a first material, the at least second layer is made of a second material different from the first material. The dielectric layer stack is patterned to form a staircase-shaped dielectric layer stack. An ion implantation process is performed to the epitaxial layer by using the staircase-shaped dielectric layer stack.

A semiconductor device includes a gate structure, a drift region, a source region, a drain region, a first doped region, and a second doped region. The gate structure is over a semiconductor substrate. The drift region is in the semiconductor substrate and laterally extends past a first side of the gate structure. The source region is in the semiconductor substrate and adjacent a second side of the gate structure opposite the first side. The drain region is in the drift region. The first doped region is in the drift region and between the drain region and the gate structure. The second doped region is within the drift region. The second doped region forms a P-N junction with the first doped region at a bottom surface of the first doped region.

A semiconductor device includes a chip formed by a wide bandgap semiconductor and having a principal surface on which a semiconductor region of a first conductivity type is formed, a base impurity region of a second conductivity type formed in a surface layer portion of the semiconductor region, a first impurity region formed in a surface layer portion of the base impurity region, and a second impurity region of a conductivity type opposite to that of the first impurity region formed in the surface layer portion of the base impurity region, the second impurity region being adjacent to the first impurity region in a first direction, wherein the second impurity region is formed in a band shape extending in a second direction orthogonal to the first direction, and includes a projection portion selectively protruding toward the first impurity region in the first direction.