A method for manufacturing a semiconductor device includes: forming conductive interconnects spaced apart from each other and protruding upwardly from an upper surface of a dielectric layer, so as to form trenches among the conductive interconnects; forming functionalized molecules such that functionalized molecules are bonded to the upper surface of the dielectric layer so as to form a self-assembled monolayer filled in the trenches; subjecting the functionalized molecules to a rearrangement treatment so as to permit the functionalized molecules to be evenly bonded on the upper surface of the dielectric layer; forming an etch stop layer on the conductive interconnects and the self-assembled monolayer; and removing the self-assembled monolayer to form air gaps so that two adjacent ones of the conductive interconnects are spaced apart from each other by a corresponding one of the air gaps.

A film forming method includes: a preparation process of preparing a substrate having a surface from which a first film without containing silicon and a second film are exposed; a first film formation process of forming a self-assembled monolayer, which has a fluorine-containing functional group and inhibits formation of a third film containing silicon, on the first film; a second film formation process of forming the third film on the second film; a modification process of decomposing the self-assembled monolayer by plasma using a gas containing hydrogen and nitrogen while maintaining a temperature of the substrate to be 70 degrees C. or lower, so that a side portion of the third film, which is formed in a vicinity of the self-assembled monolayer, is modified into ammonium fluorosilicate by active species contained in the decomposed self-assembled monolayer; and a removal process of removing the ammonium fluorosilicate.

An integrated circuit includes (i) a first transistor device having a first source or drain region coupled to a first source or drain contact, and a first gate electrode, (ii) a second transistor device having a second source or drain region coupled to a second source or drain contact, and a second gate electrode, (iii) a first dielectric material above the first and second source or drain contacts, (iv) a second dielectric material above the first and second gate electrodes, (v) a third dielectric material above the first and second dielectric materials, and (vi) an interconnect feature above and conductively coupled to the first source or drain contact. In an example, the interconnect feature comprises an upper body of conductive material extending within the third dielectric material, and a lower body of conductive material extending within the first dielectric material, with an interface between the upper and lower bodies.

Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material.

A method for forming an interconnect structure includes filling a hole through a dielectric layer with ruthenium using a deposition-etch-deposition (DED) process, forming a ruthenium layer over the dielectric layer, and forming a conductive feature from the ruthenium layer with a subtractive process. One or more etch steps of the DED process remove isolated ruthenium nuclei deposited over the dielectric layer by deposition steps of the DED process.

A semiconductor structure is provided. The semiconductor structure includes a substrate and a metallization structure over the substrate. The metallization structure includes a plurality of metal layers, a metal-ion-containing dielectric layer over at least one of the metal layers, and a conductive via laterally surrounded by the metal-ion-containing dielectric layer. A method of manufacturing a semiconductor structure is also provided.

A substrate processing method includes: preparing a substrate having a pattern, which includes a metal-containing layer formed on a base layer and a dielectric layer formed on the metal-containing layer; supplying a modifying gas into a processing container and selectively modifying the metal-containing layer at a sidewall of a hole or groove in the pattern; and supplying a processing gas including a carbon-containing gas into the processing container to generate plasma, and forming a graphene film selectively on the metal-containing layer at the sidewall by using the generated plasma.

A semiconductor device includes a plurality of conductive lines, a protection layer and an isolation layer. The conductive lines are spaced apart from each other. The protection layer conformally covers the conductive lines. The isolation layer covers the protection layer. Ability of the protection layer to endure stress is better than ability of the isolation layer to endure stress.

A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.

Embodiments provide a method and resulting structure that includes forming an opening in a dielectric layer to expose a metal feature, selectively depositing a metal cap on the metal feature, depositing a barrier layer over the metal cap, and depositing a conductive fill on the barrier layer.