A method of processing a substrate that includes: forming a conformal etch stop layer (ESL) over a staircase pattern of the substrate, the staircase pattern including staircases, each of the staircases including a conductive surface; forming a dielectric layer over the ESL; planarizing a top surface of the dielectric layer; forming a patterned hardmask over the dielectric layer; and etching the dielectric layer selectively to the ESL using the patterned hardmask as an etch mask to form a plurality of recesses, each of the plurality of recesses landing on each of the staircases, the ESL protecting the conductive surface from the etching, the etching including exposing the substrate to a plasma generated from a process gas including a fluorocarbon, O.sub.2, and WF.sub.6, a flow rate of WF.sub.6 being between 0.01% and 1% of a total gas flow rate of the process gas.

A manufacturing method of a semiconductor structure is provided. The method includes following steps. A substrate is provided, and the substrate has a first array region, a second array region, and a periphery region. A first lower conductive layer is formed on the substrate, the first lower conductive layer continuously has a first portion in the first array region, a second portion in the second array region, and a third portion in the periphery region. The first portion of the first lower conductive layer and the second portion of the first lower conductive layer are removed. A second lower conductive layer is formed on the substrate. The second lower conductive and the first lower conductive layer comprise the same material such that the second lower conductive and the first lower conductive layer form a lower conductive layer collectively.

A semiconductor device includes a conductive structure, a first dielectric layer, a second dielectric layer and a liner layer. The conductive structure is located on a substrate. The first dielectric layer covers the conductive structure and the substrate. The second dielectric layer is located on the first dielectric layer. An air gap is present in the first dielectric layer and the second dielectric layer, and is located above the conductive structure. The liner layer covers and surrounds a middle portion of the air gap.

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a base structure, a bit line structure and a spacer. The bit line structure is disposed over the base structure. The spacer is disposed around the bit line structure, and includes a first layer, a second layer and a third layer. The third layer is disposed over the second layer. A width of the third layer is substantially equal to a width of the second layer.

In an embodiment, a device includes: a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a first conductive feature extending through the first ILD; a first etch stop layer over the first conductive feature and the first ILD, the first etch stop layer being a first dielectric material; a second ILD over the first etch stop layer; a contact having a first portion extending through the second ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature; and a first protective layer surrounding the second portion of the contact, the first portion of the contact being free from the first protective layer, the first protective layer being a second dielectric material, the second dielectric material being different from the first dielectric material.

A method of manufacturing a semiconductor device includes providing a structure including a first insulating pattern and a metal pattern disposed on a substrate, performing a cleaning process on the structure, exposing the structure to a reducing agent, forming, selectively, a passivation layer on the metal pattern, forming, selectively, a second insulating pattern on the first insulating pattern, and performing thermal processing on the structure.

Semiconductor devices including a capacitor and methods of fabricating the semiconductor devices are disclosed. A method of fabricating a semiconductor device including a capacitor includes forming an underlayer structure including a substrate onto which metal is patterned within a first dielectric material, wherein the patterned metal forms a first metal surface of the capacitor; forming a middle layer of a second dielectric material above the underlayer structure; forming an upper layer of a third dielectric material above the middle layer; etching a supervia though the upper layer and into the middle layer, wherein the supervia hangs in the second dielectric material of the middle layer above the patterned metal forming the first metal surface of the capacitor; and performing barrier deposition and metal electroplating in the supervia, wherein the supervia forms a second metal surface of the capacitor above the first metal surface.

A biological sensing system, comprising a microelectrode array having a plurality of islands that are thermally isolated from each other and are interconnected by flexible nano-scale wires. An embedded complementary metal oxide semiconductor (CMOS) instrumentation amplifier and wireless communication circuitry may be operatively connected to the microelectrode array and embedded within input/output pads connected to the wires at the periphery of the array.

A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.

A connection structure for an integrated circuit includes: a 1.sup.st layer including a 1.sup.st metal line; a 2.sup.nd layer, above the 1.sup.st layer, including a 1.sup.st via; and a 3.sup.rd layer, above the 2.sup.nd layer, including a 2.sup.nd metal line connected to the 1.sup.st metal line through the 1.sup.st via, wherein the 1.sup.st via comprises a spacer structure at a side of an upper portion of the 1.sup.st via, the spacer structure comprising an insulation material.