Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a low-k dielectric layer, a high-k dielectric layer, a p-type work function metal layer, an n-type work function metal layer, a silicon oxide scap layer, and a glue layer; and a continuous tungsten (W) cap over the gate structure that was formed by the gate structure being pretreated, W material being deposited and etched back, the scap layer being etched, additional W material being deposited, and unwanted W material being removed. A semiconductor fabrication method includes: receiving a gate structure; pretreating the gate structure; depositing W material on the gate structure; etching back the W material; etching the scap layer; depositing additional W material; and removing unwanted W material.

Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

A semiconductor structure and method of forming the same are provided. The semiconductor structure has a conductive structure. The semiconductor structure includes a first conductive line, a second conductive line, a third conductive line and a conductive via. The first conductive line and the second conductive line are located in a first dielectric layer and extend along a first direction. The first conductive line and the second conductive line are spaced from each other by the first dielectric layer therebetween. The third conductive line is located in a second dielectric layer and extends along a second direction. The conductive via is vertically between the first conductive line and the third conductive line, and between the second conductive line and the third conductive line. The conductive via, in a vertical direction, is overlapped with a portion of the first dielectric layer that is laterally between the first conductive line and the second conductive line.

A method for forming an integrated circuit. The method includes providing a semiconductor structure comprising: (i) two transistors, (ii) a gate on the channel of the transistor, (iii) contacts coupled to each transistor, (iv) a dielectric layer over the two transistors, the gate, and the contacts, (v) a first conductive line arranged within a first metallization level and extending along a first direction, (vi) a first conductive via connecting the first conductive line with a first contact of a transistor, and (vii) a second conductive via connecting the first conductive line with a second contact of a transistor. The method also includes recessing the first dielectric layer, providing spacers along the first conductive line, depositing a second dielectric layer on the first dielectric layer, forming an opening in the second dielectric layer and first dielectric layer, and providing a conductive material in the opening, thereby forming a third conductive via.

A semiconductor device includes a substrate, a gate trench in the substrate, a gate insulating film in the gate trench, a titanium nitride (TiN)-lower gate electrode film on the gate insulating film, the titanium nitride (TiN)-lower gate electrode film including a top surface, a first side surface, and a second side surface opposite the first side surface, a polysilicon-upper gate electrode film on the titanium nitride (TiN)-lower gate electrode film, and a gate capping film on the polysilicon-upper gate electrode film. A center portion of the top surface of the titanium nitride (TiN)-lower gate electrode film overlaps a center portion of the polysilicon-upper gate electrode film in a direction that is perpendicular to a top surface of the substrate, and each of the first side surface and the second side surface of the titanium nitride (TiN)-lower gate electrode film is connected to the gate insulating film.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first and a second transistor; a power rail via between the first and the second transistor; and a backside via below the power rail via and below the first and the second transistor, where the backside via has a first portion directly contacting the power rail via and a second portion around the first portion, and a top surface of the first portion is above a top surface of the second portion. A method of forming the same is also provided.

The present disclosure relates to a method, which includes forming a patterned mask layer having an opening disposed on a first surface of a substrate; performing a cyclic etching and deposition processes from the first surface to form a recess corresponding to the opening and a liner layer disposed thereon; performing a first removal process to remove the liner layer for exposing a portion of the substrate in the recess; and performing a trimming process to remove the portion of the substrate in the recess.

A semiconductor device includes a logic device including a first portion of a first substrate extending vertically below a first source/drain region, a second portion of the first substrate extending vertically below a second source/drain region, a first shallow trench isolation (STI) extending vertically and isolating the first portion of the first substrate and the second portion of the first substrate, a backside power delivery network (BSPDN) below the logic device, a first dielectric layer extending vertically through sidewalls of a backside contact. The first dielectric layer isolates the backside contact from the first portion of the first substrate and the second portion of the first substrate.

A semiconductor device includes a shallow trench isolation (STI), a first well region connected to the insulating region and the STI on a first side, a second well region connected to the insulating region and the STI on a second side, and a backside contact including an upper portion, a lower portion, and a middle portion connecting the upper portion and the lower portion. A shape and a profile of the insulating region is same as a shape and a profile of the middle portion.

A method is disclosed for producing an array of parallel conductive lines in a first level of a multilevel interconnect structure of a semiconductor component. The lines are produced by direct etching (a conductive layer is produced), a hardmask line pattern is formed on the conductive layer and the line pattern is transferred to the conductive layer by etching the conductive layer relative to the hardmask lines. The hardmask lines are reduced in width prior to the pattern transfer. The width reduction is done at intended via locations. Local hardmask pillars are produced on the hardmask lines prior to the width reduction step, so that the original line width is maintained at the intended via locations. As a result, the width of the conductive lines obtained after the pattern transfer is smaller compared to conventional configurations, except in local areas corresponding to the locations of interconnect vias.