A method includes forming a fin protruding from a substrate, forming a gate structure across the fin, forming an epitaxial feature over the fin, depositing a dielectric layer covering the epitaxial feature and over sidewalls of the gate structure, performing an etching process to form a trench, the trench dividing the gate structure into first and second gate segments and extending into a region of the dielectric layer, forming a dielectric feature in the trench, recessing a portion of the dielectric feature located in the region, selectively etching the dielectric layer to expose the epitaxial feature, and depositing a conductive feature in physical contact with the epitaxial feature and directly above the portion of the dielectric feature.

An integrated circuit structure includes a metal line that has an upper surface defining a periphery; a dielectric spacer that is formed around the periphery of the upper surface of the metal line; and a metal via that contacts the metal line and the dielectric spacer adjacent to the periphery of the upper surface. A method for making a semiconductor structure includes depositing a spacer around the periphery of an upper surface of a metal line; and depositing a via onto the metal line, so that a part of the via overlaps the spacer.

The present disclosure relates to a method of forming an interconnect structure that eliminates a separate deep via patterning process to simplify the fabrication process. In some embodiments, a first dielectric layer is formed over a first metal line and patterned to form a through-hole exposing a first contact region of the first metal line. A second dielectric layer is deposited and patterned to form a first via-hole connecting to the through-hole and a second via-hole exposing a second contact region of the second metal line from a layout view. A first via is formed on the first contact region extending to a first upper surface of the second dielectric layer, and a second via is formed on the second contact region extending to a second upper surface of the second dielectric layer.

Semiconductor structures and methods of forming the same are provided. In one embodiment, a semiconductor structure includes an active region over a substrate, a gate structure disposed over the active region, and a gate contact that includes a lower portion disposed over the gate structure and an upper portion disposed over the lower portion.

In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.

Methods, systems, and devices for techniques to manufacture inter-layer vias are described. In some examples, a manufacturing process for a via to one or more metal lines within an integrated circuit may not include forming a metal pad for the via. For example, the manufacturing process may include forming a layer of dielectric material over a set of metal lines. The manufacturing process may further include forming a cavity through the dielectric layer (e.g., using an etching procedure), exposing the upper surfaces and sidewalls of one or more metal lines of the set. Subsequently, the via may be formed by depositing a conductive material within the cavity. In some cases, the conductive material may be deposited to contact the sidewalls of the one or more metal lines. Such an assembly may establish electrical connection to other electrical components of the integrated circuit.

A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and conductive rails laterally adjacent to the conductive structures of the stack structure. The conductive rails comprise a material composition that is different than a material composition of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

A method of forming a semiconductor structure includes forming a semiconductor device over a substrate, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, where the connection-level metal interconnect structure is electrically connected to a node of the semiconductor device and is embedded in the connection-level dielectric layer, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure containing cobalt from a bottom of the via portion of the integrated line-and-via cavity without completely filling a line portion of the integrated line-and-via cavity, and forming a copper-based conductive line structure that contains copper at an atomic percentage that is greater than 90% in the line portion of the integrated line-and-via cavity on the conductive via structure.

The semiconductor stacked package including a semiconductor die. The semiconductor die includes a substrate, a transistor, and a through-silicon-via (TSV) structure. The transistor is over the substrate. The TSV structure penetrates the substrate and comprises a first conductive layer, a second conductive layer, and a dielectric layer. The dielectric layer is between the first conductive layer and the second conductive layer. The method of manufacturing the same includes the following steps: forming a via hole in a substrate; forming a first conductive layer in the via hole; forming a dielectric layer in the via hole and over the first conductive layer; forming a second conductive layer in the via hole and over the dielectric layer; and forming a transistor over the substrate. The first conductive layer, the dielectric layer, and the second conductive layer collectively form a through-silicon-via (TSV) structure.

A method for manufacturing a semiconductor structure includes: forming first conducting portions that are spaced apart from each other on a base structure; forming isolation elements, each of which includes a dielectric lower portion and an etching-resistant upper portion covering the dielectric lower portion, the etching-resistant upper portion being made of an etching-resistant material different from a dielectric material of the dielectric lower portion, each of the isolation elements being isolated and exposed from two adjacent ones of the first conducting portions; sequentially forming an etch stop layer and an interlayer dielectric over the first conducting portions and the isolation elements; forming a cavity which extends through the etch stop layer and the interlayer dielectric, and which exposes one of the first conducting portions; and filling the cavity with a second conducting portion.