Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a low-k dielectric layer, a high-k dielectric layer, a p-type work function metal layer, an n-type work function metal layer, a silicon oxide scap layer, and a glue layer; and a continuous tungsten (W) cap over the gate structure that was formed by the gate structure being pretreated, W material being deposited and etched back, the scap layer being etched, additional W material being deposited, and unwanted W material being removed. A semiconductor fabrication method includes: receiving a gate structure; pretreating the gate structure; depositing W material on the gate structure; etching back the W material; etching the scap layer; depositing additional W material; and removing unwanted W material.

Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

A method for semiconductor manufacturing includes removing an oxide layer disposed over a conductive feature, flowing a gallium precursor over the conductive feature, and depositing a metal over the conductive feature after flowing the gallium precursor. The conductive feature is adjacent to a dielectric feature. The metal is deposited selectively over the conductive feature relative to the dielectric feature.

A high voltage semiconductor package includes a semiconductor device. The semiconductor device includes a high voltage semiconductor transistor chip having a front side and a backside. A low voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. A high voltage load electrode is disposed on the backside of the semiconductor transistor chip. The semiconductor package further includes a dielectric inorganic substrate. The dielectric inorganic substrate includes a pattern of first metal structures running through the dielectric inorganic substrate and connected to the low voltage load electrode, and at least one second metal structure running through the dielectric inorganic substrate and connected to the control electrode. The front side of the semiconductor transistor chip is attached to the dielectric inorganic substrate by a wafer bond connection, and the dielectric inorganic substrate has a thickness of at least 50 m.

The present disclosure describes a method for forming an interconnect structure. The method can include forming a first layer of insulating material on a substrate, forming a via recess within the layer of insulating material, filling the via recess with a layer of conductive material, selectively growing a second layer of insulating material over the first layer of insulating material, and opening the second layer of insulating material to the layer of conductive material while growing the second layer of insulating material.

A method includes forming a fin protruding from a substrate, forming a gate structure across the fin, forming an epitaxial feature over the fin, depositing a dielectric layer covering the epitaxial feature and over sidewalls of the gate structure, performing an etching process to form a trench, the trench dividing the gate structure into first and second gate segments and extending into a region of the dielectric layer, forming a dielectric feature in the trench, recessing a portion of the dielectric feature located in the region, selectively etching the dielectric layer to expose the epitaxial feature, and depositing a conductive feature in physical contact with the epitaxial feature and directly above the portion of the dielectric feature.

A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.

Methods, systems, and devices for techniques to manufacture inter-layer vias are described. In some examples, a manufacturing process for a via to one or more metal lines within an integrated circuit may not include forming a metal pad for the via. For example, the manufacturing process may include forming a layer of dielectric material over a set of metal lines. The manufacturing process may further include forming a cavity through the dielectric layer (e.g., using an etching procedure), exposing the upper surfaces and sidewalls of one or more metal lines of the set. Subsequently, the via may be formed by depositing a conductive material within the cavity. In some cases, the conductive material may be deposited to contact the sidewalls of the one or more metal lines. Such an assembly may establish electrical connection to other electrical components of the integrated circuit.

A semiconductor package includes a laminate package body and a die assembly embedded within the laminate package body. The laminate package body includes a plurality of laminate dielectric layers stacked on top of one another and metallization layers interposed between the laminate dielectric layers. The die assembly includes a thermally conductive substrate that includes a planar upper surface, a semiconductor die mounted on the planar upper surface of the thermally conductive substrate, and an electrically insulating thickness-matching layer formed on the planar upper surface of the thermally conductive substrate and surrounding the semiconductor die. An upper surface of the electrically insulating thickness-matching layer is substantially coplanar with an upper surface of the semiconductor die. The upper surface of the electrically insulating thickness-matching layer and the upper surface of the semiconductor die form an upper surface of the die assembly.