A package substrate and a semiconductor package including the same are provided. The semiconductor package includes a package substrate including a base having a front side and a back side, rear pads below the back side of the base, lower connection patterns below the rear pads and in contact with the rear pads, first and second front pads on the front side of the base, a first support pattern on the front side of the base having a thickness greater than a thickness of each of the first and second front pads, and a protective insulating layer on the front side of the base and having openings exposing the first and second front pads respectively, and on an upper surface and a side surface of the first support pattern; a lower semiconductor chip on the protective insulating layer of the package substrate, spaced apart from the first support pattern in a horizontal direction; and a first upper semiconductor chip on the package substrate vertically overlapping the lower semiconductor chip and the first support pattern.

The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a first substrate, a first chip, a second chip, a first heat conductor and a second heat conductor, wherein the first substrate includes a cavity; the first chip is embedded in the cavity and includes a first connecting surface and a first heat-conducting surface that face away from each other; the second chip is disposed on a side of the first connecting surface and electrically connected to the first chip, a side of the second chip distal from the first chip includes a second heat-conducting surface on a side; and the first heat conductor is connected to the first heat-conducting surface, and the second heat conductor is connected to the second heat-conducting surface. The first substrate includes a third connecting surface that is flush with the first connecting surface.

A method of forming a wafer-level package includes singulating a wafer into a plurality of reconstituted integrated circuit dies, affixing a carrier to a front side of the plurality of integrated circuit dies, and forming a laser direct structuring (LDS) activatable resin over a back side of the plurality of integrated circuit dies, over side edges of the plurality of integrated circuit die, and over adjacent portions of the carrier. Desired areas of the LDS activatable resin are activated to form conductive areas within the LDS activatable resin, at least one of the conductive areas associated with each integrated circuit die being formed to contact a respective pad of that integrated circuit die and to run alongside to and in contact with a side of the LDS activatable resin in contact with a side edge of that integrated circuit die.

A substrate includes a base plate made of an insulating material, a first electrically conductive layer disposed on a first side of the base plate, and a second electrically conductive layer disposed on a second side of the base plate. The first electrically conductive layer has a stepped surface, the stepped surface including a plurality of steps at different heights above the base plate.

A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die, a package substrate, and at least one bonding wire. The package substrate includes a dam structure to define a space where the semiconductor die is placed. The bonding wire is electrically connected between the semiconductor die and the package substrate.

An electronic structure, an electronic package and a manufacturing method thereof are provided, in which a carrier and an adhesive layer are used to support or fix the electronic structure and the electronic package, and double carriers are used to support or fix the electronic structure and the electronic package, thereby avoiding the warpage problem of the electronic structure and the electronic package.

A method includes forming a first photoresist layer on a dielectric layer; performing a first light-exposure process on the first photoresist layer using a first photolithography mask, wherein during the first light-exposure process, a first region the first photoresist layer is blocked from being exposed, a second region of the first photoresist layer is exposed, and a third region of the first photoresist layer is exposed, wherein the second region encircles the first region and the third region encircles the second region; performing a second light-exposure process on the first photoresist layer using a second photolithography mask, wherein during the second light-exposure process, the first region of the first photoresist layer is exposed, the second region of the first photoresist layer is exposed, and the third region of the first photoresist layer is blocked from being exposed; and developing the first photoresist layer.

A semiconductor package has a first semiconductor package which includes a first redistribution structure, a first semiconductor chip on a lower surface of the first redistribution structure, a first encapsulant on at least a portion of the first semiconductor chip, a second redistribution structure on the first encapsulant, and a conductive post electrically connecting the first redistribution structure and the second redistribution structure through the first encapsulant; and a second semiconductor package which is on an upper surface of the first redistribution structure and comprises a third redistribution structure, a second semiconductor chip on the third redistribution structure, and a second encapsulant on at least a portion of the second semiconductor chip, wherein the first encapsulant integrally covers each of a lower surface and a side surface of the first semiconductor chip.

A semiconductor package structure includes a redistribution structure layer, at least one chip, an encapsulant, and multiple solder balls. The redistribution structure layer includes multiple first connectors located on a first side. Each first connector includes a connecting pad, a soldering pad, and multiple conductive blind holes located between the connecting pad and the soldering pad. The conductive blind holes are disposed separately from each other and connect the connecting pad and the soldering pad. The chip is disposed on a second side of the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the second side and at least covers the chip and the second side. The solder balls are disposed on the first side of the redistribution structure layer and electrically connected to the redistribution structure layer. The solder balls are respectively connected to the connecting pad of each first connector.

An electronic package and a manufacturing method thereof are provided. The electronic package includes an electronic component and a shielding layer. The electronic component has an active surface, an inactive surface opposite to the active surface, and a side surface connecting the active surface and the active surface. The shielding layer is disposed on the electronic component and directly contacts and completely covers the inactive surface and the side surface. The shielding layer is formed directly on the surface of the electronic component, thereby shielding electromagnetic interference, reducing the size of the electronic package, and lowering production costs.