Patent classifications
H10W74/15
Semiconductor package
A semiconductor package comprises a base substrate, a first semiconductor chip on the base substrate, a first dam structure which overlaps a corner of the first semiconductor chip from a plan view and is placed on the base substrate and a first fillet layer which is placed vertically between the base substrate and the first semiconductor chip, and vertically between the first dam structure and the first semiconductor chip.
Semiconductor devices and methods of manufacturing semiconductor devices
In one example, an electronic device comprises a substrate comprising a conductive structure and an inner side and an outer side, a first electronic component over the inner side of the substrate and coupled with the conductive structure, a lid over the substrate and the first electronic component and comprising a first hole in the lid, and a thermal interface material between the first electronic component and the lid. The thermal interface material is in the first hole. Other examples and related methods are also disclosed herein.
Semiconductor package and package-on-package having different wiring insulating layers surrounding differential signal wiring layers
A semiconductor package is provided. The semiconductor package includes: a lower equipotential plate provided in a lower wiring layer; an upper equipotential plate provided in an upper wiring layer; a pair of differential signal wiring lines provided in a signal wiring layer that is between the lower equipotential plate and the upper equipotential plate, wherein the pair of differential signal wiring lines includes a first differential signal wiring line and a second differential signal wiring line which are spaced apart from each other and extend in parallel; and a wiring insulating layer surrounding the pair of differential signal wiring lines, and filling between the signal wiring layer, the lower wiring layer, and the upper wiring layer. The wiring insulating layer includes a first wiring insulating layer surrounding the pair of differential signal wiring lines, and a second wiring insulating layer, and the first wiring insulating layer and the second wiring insulating layer include different materials.
Electronic package and manufacturing method thereof
An electronic package and a manufacturing method thereof are provided, in which a cover is disposed on a carrier structure having an electronic element, and the electronic element is covered by the cover. A magnetic conductive member is arranged between the cover and the electronic element, and an air gap is formed between the magnetic conductive member and the cover to enhance the shielding effect of the electronic package.
Semiconductor package
A semiconductor package includes a semiconductor chip including a semiconductor substrate having an active layer, ground chip pads on the semiconductor substrate, and signal chip pads on the semiconductor substrate and a package substrate supporting the semiconductor chip, the package substrate including a substrate insulating layer, a plurality of signal line patterns extending in the substrate insulating layer and electrically connected to the signal chip pads, and a plurality of ground line patterns extending in the substrate insulating layer at a same level as a level of the plurality of signal line patterns and electrically connected to the ground chip pads. At least one of the plurality of ground line patterns extends between the plurality of signal line patterns.
Integrated circuit chip and semiconductor package
An integrated circuit chip includes; a package substrate including a first signal ball, a first semiconductor chip on the package substrate, a second semiconductor chip on the first semiconductor chip, a first bump disposed between the package substrate and the first semiconductor chip and electrically connected to the first signal ball, and a second bump disposed between the first semiconductor chip and the second semiconductor chip and electrically connected to the first signal ball, wherein during a first mode, the first signal ball receives a signal from the first semiconductor chip through the first bump and receives a signal from the second semiconductor chip through the second bump.
Electronic package and electronic structure thereof
An electronic package is provided in which an electronic structure is bonded onto a carrier structure via a plurality of conductive elements, where each of the conductive elements is connected to a single contact of the electronic structure via a plurality of conductive pillars. Therefore, when one of the conductive pillars fails, each of the conductive elements can still be electrically connected to the contact via the other of the conductive pillars to increase electrical conductivity.
INTEGRATED CIRCUIT PACKAGING WITH CONDUCTIVE FILM
A current sensor integrated circuit (IC) package is flip-chip bonded using a conductive film to connect the IC circuit bond pads to the lead frame. A conductive film is positioned between the die surface of a semiconductor die and at least one signal lead of the lead frame. The conductive film is conductive in a first direction between the die and the signal lead and nonconductive in other directions. The conductive film is further configured to control a gap height between the die and the lead frame to reduce die tilt, thus improving the sensitivity and performance consistency of the package.
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Provided is a semiconductor package including a plurality of first semiconductor chips respectively including a first semiconductor substrate and a plurality of first through electrodes penetrating the first semiconductor substrate, a second semiconductor chip on the plurality of first semiconductor chips, the second semiconductor chip including a second semiconductor substrate and a plurality of second through electrodes penetrating the second semiconductor substrate, a third semiconductor chip on the second semiconductor chip, the third semiconductor chip including a third semiconductor substrate and a plurality of third through electrodes penetrating the third semiconductor substrate, and a first encapsulation material on the plurality of first semiconductor chips, a planar shape of the second semiconductor chip is greater than a planar shape of each first semiconductor chip of the plurality of first semiconductor chips, and a planar shape of the third semiconductor chip is greater than the planar shape of the second semiconductor chip.
MULTI-CHIP PACKAGING
An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.