A component carrier includes a stack with electrically conductive layer structures and at least one electrically insulating layer structure. The electrically conductive layer structures have a higher density connection region and a lower density connection region, and a first component and a second component which are surface mounted on the stack. The first component and the second component are electrically coupled with each other by the higher density connection region.

A semiconductor die includes semiconductor devices located on a semiconductor substrate, metal-insulator-metal corner structures overlying the semiconductor devices and located in corner regions of the semiconductor die. Metal-insulator-metal corner structures are located in the corner regions of the semiconductor die. Each of the metal-insulator-metal corner structures has a horizontal cross-sectional shape selected from a triangular shape and a polygonal shape including a pair of laterally-extending strips extending along two horizontal directions that are perpendicular to each other and connected to each other by a connecting shape.

The present disclosure relates to a power module. The power module includes a first die having an upper surface; a second die adjacent to the first die and having an upper surface at an elevation different from the upper surface of the first die; a circuit structure disposed over the first die and the second die and having a surface; and an elastic structure connecting the first die and the second die to the first circuit structure and configured to keep the surface of the circuit structure being substantially horizontal.

A semiconductor module may include a package substrate including a first surface and an opposite second surface, a semiconductor chip on the first surface of the package substrate, a plurality of pads on the second surface of the package substrate, and a plurality of solder balls connected to the plurality of pads, respectively, where the package substrate may include a slit in or on the second surface, at least a portion of the slit is disposed between the plurality of solder balls, the slit is spaced apart from the plurality of pads, and a filling layer is in the slit.

A semiconductor package component which has an outer profile including an oblique package edge obliquely interconnecting between two adjacent side walls. The semiconductor package component includes a first redistribution layer (RDL) unit, a chip unit, a dummy die unit, an encapsulation layer, and a second RDL unit. The chip unit is disposed on the first RDL unit. The dummy die unit includes a dummy die that is disposed on the first RDL unit, and has a dummy die edge which extends in a direction parallel to the oblique package edge. A method for making the semiconductor package component is also disclosed.

Bonded die structures and methods of fabricating bonded die structures with improved stress distribution. A bonded die structure may include a second die bonded to a first die. The sizes, shapes and/or relative position of the first die with respect to the second die may be configured to minimize stress concentrations in the bonded die structure. In some embodiments, a length dimension of a corner region of the second die may be less than a length dimension of the adjacent corner region of the first die, which may aid in redistributing stress away from the corner of the first die. An offset distance between the corner of the second die and the corner of the first die may also be controlled to minimize stress applied to the corner of the first die along a vertical direction. Accordingly, crack formation may be reduced, and device performance and yields may be improved.

A method includes removing an oxide layer from select areas of a surface of a metal structure of a lead frame to create openings that extend through the oxide layer to expose portions of the surface of the metal structure. The method further includes attaching a semiconductor die to the lead frame, performing an electrical connection process that electrically couples an exposed portion of the surface of the metal structure to a conductive feature of the semiconductor die, enclosing the semiconductor die in a package structure, and separating the electronic device from the lead frame. In one example, the openings are created by a laser ablation process. In another example, the openings are created by a chemical etch process using a mask. In another example, the openings are created by a plasma process.

A package structure includes a die, an encapsulant laterally encapsulating the die, a warpage control material disposed over the die, and a protection material disposed over the encapsulant and around the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.

A method of manufacturing a package structure at least includes the following steps. An encapsulant laterally is formed to encapsulate the die and the plurality of through vias. A plurality of first connectors are formed to electrically connect to first surfaces of the plurality of through vias. A warpage control material is formed over the die, wherein the warpage control material is disposed to cover an entire surface of the die. A protection material is formed over the encapsulant and around the plurality of first connectors and the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.

Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.