The technology of this application relates to a board-level structure that includes an upper-layer substrate, a lower-layer substrate, and a plurality of support members that are supported between the upper-layer substrate and the lower-layer substrate. In an example embodiment, a gap exists between the upper-layer substrate and the lower-layer substrate, the gap includes at least one first gap region and at least one second gap region, the first gap region and the second gap region are spaced, a spaced region between the first gap region and the second gap region does not include the first gap region or the second gap region, and a maximum vertical distance between the upper-layer substrate and the lower-layer substrate in the first gap region is less than a minimum vertical distance between the upper-layer substrate and the lower-layer substrate in the second gap region.

A wiring board that facilitates narrowing a pitch of bonding terminals used for bonding to a semiconductor chip, providing finer wiring in a substrate and reducing cost, and is capable of achieving high connection reliability. A composite wiring board includes: a first wiring board; a second wiring board facing the first wiring board and bonded to the first wiring board, a distance from the second wiring board to the first wiring board being greater at a peripheral part than at a center part of the second wiring board; and a sealing resin layer interposed between the first wiring board and the second wiring board, the sealing resin layer covering an end face of the second wiring board.

An inner lead structure of a flexible circuit board includes a flexible substrate, a circuit layer and a dummy circuit layer. A chip mounting area defined on the flexible substrate is provided for a chip, contacting locations defined within the chip mounting area are provided for conductive elements of the chip. The circuit layer includes inner leads, ends of the inner leads are arranged on the contacting locations and provided to be electrically connected to the conductive elements. At least one of first dummy lines of the dummy circuit layer is arranged in a space between the adjacent inner leads. The space having a distance greater than 50 um is divided into multiple spaces having distances not greater than 50 um. Proportion of the spaces without the first dummy lines and having a distance greater than 50 um is less than 0.5% in all spaces.

There is provided a semiconductor device 1, comprising: a housing comprising a housing electrode 4; and at least one semiconductor chip 20 arranged within the housing; wherein the housing electrode 4 comprises a deformable portion 15, and the deformable portion 15 is configured to deform when a pressure difference between an interior and an exterior of the housing exceeds a threshold differential pressure or a temperature at the deformable portion exceeds a threshold temperature, so as to transform the housing from a hermetically sealed housing to an open housing in fluid communication with the exterior.

A method of manufacturing a semiconductor package includes: forming through-vias extending from a front side of a semiconductor substrate into the substrate; forming, on the front side of the semiconductor substrate, a circuit structure including a wiring structure electrically connected to the through-vias; removing a portion of the semiconductor substrate so that at least a portion of each of the through-vias protrudes to a rear side of the semiconductor substrate; forming a passivation layer covering the protruding portion of each of the through-vias; forming trenches recessed along a periphery of a corresponding one of the through-vias; removing a portion of the passivation layer so that one end of each of the through-vias is exposed to the upper surface of the passivation layer; and forming backside pads including a dam structure in each of the trenches, the dam structure being spaced apart from the corresponding one of the through-vias.

Semiconductor (SC) chip devices and associated methods of making are presented. The SC chips are designed to include enlarged extension semiconductor areas next to functional integrated circuit (IC) dies on these SC chips. Some variations include designing semiconductor wafers prior to fabrication so that the resultant IC dies are surrounded by the extension semiconductor areas. Other variations include processing post manufactured semiconductor wafers to expand the size of the available extension areas by including truncated pieces of IC dies that are immediately adjacent to functional working primary IC dies. These variations provide additional room for redistribution layers to fan-out from the IC dies outwards onto the extension areas.

A bonded structure is disclosed. The bonded structure can include an interconnect structure. The bonded structure can also include a first die directly bonded to the interconnect structure. The bonded structure can also include a second die mounted to the interconnect structure. The second die is spaced apart from the first die laterally along an upper surface of the interconnect structure. The second die is electrically connected with the first die at least partially through the interconnect structure. The bonded structure can further include a dielectric layer that is disposed over the upper surface of the interconnect structure between the first die and the second die.

A semiconductor package includes a package base substrate including a potential plate. An interposer is arranged on the package base substrate and comprises at least one interposer through electrode, at least one first connection bump, and at least one second connection bump. A first stacked chip unit is arranged on the interposer and comprises a first semiconductor chip and at least one second semiconductor chips arranged on the first semiconductor chip. At least one passive device unit is arranged on the package base substrate. The at least one passive device unit is spaced apart from the interposer in a horizontal direction parallel to an upper surface of the package base substrate. The at least one first connection bump is a dummy bump. The potential plate electrically connects the at least one first connection bump and a power terminal of the at least one passive device unit to each other.

A power semiconductor device includes a semiconductor structure comprising an active region, and a plurality of stress relief trenches in the semiconductor structure laterally between the active region and at least one edge of the semiconductor structure. The stress relief trenches respectively comprise opposing sidewalls and a dielectric material and/or a semiconductor material therebetween, and do not contribute to electrical conduction between first and second terminals of the power semiconductor device. Related devices and fabrication methods are also discussed.

A semiconductor device includes a support including a base member having a first main surface facing a thickness direction, a semiconductor element, and a bonding material that bonds the support and the semiconductor element. The bonding material includes a sintered metal portion and a resin portion. The support includes a metal layer located on the first main surface and having a stronger sintered bonding with the sintered metal portion than the base member. The bonding material includes a first portion in contact with the semiconductor element and the metal layer, and a second portion in contact with the semiconductor element and the base member.