A flip-chip bonding-based antenna packaging structure and its manufacturing method are provided. The flip-chip bonding-based antenna packaging structure includes a lead frame structure and a redistribution structure disposed above the lead frame structure. The redistribution structure includes a first surface and a second surface. The lead frame structure is disposed on the redistribution structure and includes a metal member, a first active element, and a passive element. The metal member includes a base portion, a first supporting portion on the base portion, and an extension portion adjacent to the first supporting portion. The extension portion extends from the base portion, and the first supporting portion is parallel to the extension portion. The first active element is disposed between the first supporting portion and the first surface. The passive element is disposed on the second surface and is electrically connected to the first active element.

A semiconductor package comprises a package substrate, a first semiconductor chip comprising a semiconductor substrate, a wiring structure on the semiconductor substrate, a connection pad at an uppermost part of the wiring structure, and a protective layer on a side surface of the connection pad, a crack reduction layer on the connection pad and the protective layer and a mold layer on the crack reduction layer, wherein a coefficient of thermal expansion of the crack reduction layer is lower than a coefficient of thermal expansion of the semiconductor substrate.

Electronic packages, die structures and methods of fabrication are described in which a recess is formed by removing material from the edges and corners of a die that may increase the risk of non-bonding or delamination. In an embodiment, a die includes a recess with a width that extends from a perimeter edge to a recessed edge, and a depth that extends from a top surface to a recess floor. In some embodiments, the recess is filled with gap fill material. In other embodiments, the recess is not filled with gap fill material.

A semiconductor package with reduced contact defect and enhanced reliability is provided. The semiconductor package includes a substrate including an insulating layer and a through-via extending through the insulating layer, a magnet within the insulating layer and spaced apart from the through-via, a semiconductor chip on the substrate, and a magnetic layer on the semiconductor chip and overlapping with at least a portion of the magnet in a vertical direction relative to an upper surface of the substrate.

A wafer-to-wafer bonding structure includes a first wafer having a first bonding layer thereon, a first main pattern region, a first scribe lane surrounding the first main pattern region, and a first alignment cavity disposed in the first bonding layer within the first main pattern region; and a second wafer having a second bonding layer bonded to the first bonding layer, a second main pattern region, a second scribe lane surrounding the second main pattern region, and a second alignment cavity disposed in the second bonding layer within the second main pattern region.

A semiconductor package according to some example embodiments may include a chip base including a main chip region and an edge region around the main chip region, a device layer on the chip base, a wiring layer on the device layer, an upper insulating stack on the wiring layer, and a trench on the edge region, the trench recessed from the upper insulating stack to the device layer, and an inner surface of the trench exposed to an outside of the semiconductor chip.

The present invention relates to a semiconductor device including: a semiconductor substrate having: an active region through which a main current flows; and a termination region around the active region; a polyimide film disposed in the active region and the termination region; and a passivation film disposed as a film underlying the polyimide film, wherein the termination region includes, in order from a side of the active region, a breakdown voltage holding region and an outermost peripheral region, the polyimide film is disposed except for a dicing remaining portion of the outermost peripheral region, and the passivation film is disposed, as the underlying film, at least in a region where the polyimide film is disposed.

A semiconductor device includes a circuit substrate, a semiconductor package, connective terminals and supports. The circuit substrate has a first side and a second side opposite to the first side. The semiconductor package is connected to the first side of the circuit substrate. The connective terminals are located on the second side of the circuit substrate and are electrically connected to the semiconductor package via the circuit substrate. The supports are located on the second side of the circuit substrate beside the connective terminals. A material of the supports has a melting temperature higher than a melting temperature of the connective terminals.

Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.

A semiconductor module, including a semiconductor chip, a sealed main body portion sealing the semiconductor chip and having a pair of attachment holes penetrating therethrough, a heat dissipation plate in contact with the sealed main body portion. The heat dissipation plate is positioned between the attachment holes in a plan view of the semiconductor module. The semiconductor module further includes a pair of rear surface supporting portions and/or a pair of front surface supporting portions protruding respectively from rear and front surfaces of the sealed main body portion. In the plan view, the heat dissipation plate is formed between the pair of attachment holes, which are in turn between the pair of rear surface supporting portions. The pair of front surface supporting portions are formed substantially between the pair of attachment holes in the plan view.