A semiconductor package includes a package substrate including a base substrate including a redistribution layer, pads disposed on first and second surfaces of the base substrate and connected to the redistribution layer, and a protective layer having a mounting region in which first openings respectively exposing first pads among the pads and a second opening exposing second pads among the pads and a portion of the second surface are disposed on the second surface; a semiconductor chip disposed on the mounting region and connected to the pads through the first openings and the second opening; and a sealing material covering a portion of the semiconductor chip and extending into the second opening. Four first openings among the first openings are respectively disposed adjacent to respective corners of the mounting region. The second opening is disposed to divide the four first openings into at least two groups.

A semiconductor package includes a connection substrate on a package substrate and has an opening that penetrates therethrough. A chip stack is on the package substrate and in the opening. A redistribution layer is on the connection substrate and the chip stack. An upper semiconductor chip is on first redistribution pads of the redistribution layer. External terminals are on a bottom surface of the package substrate. The chip stack includes a first semiconductor chip on substrate pads of the package substrate, and a second semiconductor chip on the first semiconductor chip and second redistribution pads of the redistribution layer. The redistribution layer includes a first region that overlaps the upper semiconductor chip and a second region beside the upper semiconductor chip. The first redistribution pads are on the first region. The second redistribution pads are on the second region.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes an active silicon substrate and a memory interface circuit configured to support N memory channels. The memory interface circuit has a primary interface for coupling to a host memory interface via the N memory channels. A first HBM stack of memory die is disposed on the active silicon substrate and coupled to a secondary interface of the memory interface circuit. The first HBM stack dedicated to a first subset of the N data channels and a first data transfer rate. A second HBM stack of memory die is disposed on the active silicon substrate. The second HBM stack is positioned inline with the first HBM stack and the memory interface circuit and coupled to the secondary interface of the memory interface circuit. The second HBM stack is dedicated to a second subset of the N data channels and exhibits a second data transfer rate. The first HBM stack and the second HBM stack are configured to collectively support the N channels and exhibit an aggregate data rate that is a sum of the first data rate and the second data rate.

A semiconductor device has a substrate and a first electrical interconnect structure formed over a first surface of the substrate. A second electrical interconnect structure is formed over a second surface of the substrate. An electrical component is disposed over the first surface of the substrate or over the second surface of the substrate. A first antenna is formed over the first electrical interconnect structure. A second antenna is formed over the second electrical interconnect structure. The first electrical interconnect structure has an insulating material formed over the first surface of the substrate, and a conductive via formed through the insulating material. Alternatively, the first electrical interconnect structure has an insulating layer formed over the first surface of the substrate, a conductive layer formed over the insulating layer, and a conductive via formed through the insulating layer and conductive layer.

A semiconductor package structure includes a base having a first surface and a second surface opposite thereto, wherein the base comprises a wiring structure, a first electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, a second electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, wherein the first electronic component and the second electronic component are separated by a molding material, a first hole and a second hole formed on the second surface of the base, and a frame disposed over the first surface of the base, wherein the frame surrounds the first electronic component and the second electronic component.

A system comprises: an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a power switch including a drain terminal, a source terminal, and a gate terminal; and a controller configured to detect a change in current at the source terminal of the power switch using a complex impedance of a metal trace connected to the source terminal of the power switch, and control a gate control signal to the gate terminal based on the detected change in current.

A semiconductor package, as a semiconductor package mounted on a circuit board, includes including: a body portion including a semiconductor chip, and a first surface and a second surface opposite to each other; and a structure including n insulating layers stacked on at least one of the first surface and the second surface of the body portion, wherein the semiconductor package has a predetermined target coefficient of thermal expansion (CTE), and the n insulating layers and the body portion have a thickness and a CTE satisfying a condition that an effective CTE of the semiconductor package becomes equal to the predetermined target CTE.

This document discloses techniques, apparatuses, and systems relating to a package substrate for a semiconductor device. A semiconductor device assembly is described that includes a packaged semiconductor device having one or more semiconductor dies coupled to a package-level substrate. The package-level substrate has a first surface at which first contact pads are disposed in a first configuration. The packaged semiconductor device is coupled with an additional package-level substrate that includes a second surface having second contact pads disposed in the first configuration and a third surface having third contact pads disposed in a second configuration different from the first configuration. The additional package-level substrate includes circuitry coupling the second contact pads the third contact pads to provide connectivity at the third contact pads. In doing so, an adaptively compatible semiconductor device may be assembled.

A package for a semiconductor device includes a metal base plate, a wall portion, a first metal film, and a lead portion. The base plate has a first region and a second region surrounding the first region. The wall portion has a first frame body comprising metal and a second frame body comprising resin. The first frame body is provided on the second region. The second frame body is provided on the first frame body. The first metal film is provided on the second frame body. The lead portion is conductively bonded to the first metal film. The first frame body is conductively bonded to the base plate. A thickness of the first frame body in a first direction that is a direction in which the first frame body and the second frame body are arranged is larger than a thickness of the first metal film in the first direction.

A manufacturing method of a package structure includes: forming a redistribution layer on a top surface of a glass substrate; forming a protective layer on the top surface of the glass substrate; cutting the glass substrate and the protective layer such that the glass substrate has a cutting edge, in which a crack is formed in the cutting edge of the glass substrate; and heating the protective layer such that a portion of the protective layer flows towards a bottom surface of the glass substrate to cover the cutting edge of the glass substrate and fill the crack in the cutting edge of the glass substrate.