An embodiment method includes: forming a dielectric-containing substrate over a semiconductor substrate; forming a stack of first semiconductor layers and second semiconductor layers over the dielectric-containing substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack; patterning the first semiconductor layer and the second semiconductor layers into a fin structure such that the fin structure includes sacrificial layers including the second semiconductor layers and channel layers including the first semiconductor layers; forming source/drain features adjacent to the sacrificial layers and the channel layers; removing the sacrificial layers of the fin structure so that the channel layers of the fin structure are exposed; and forming a gate structure around the exposed channel layers, wherein the dielectric-containing substrate is interposed between the gate structure and the semiconductor substrate.

The method provides for the growth of an epitaxial layer (200) made of a first semiconductor material on a substrate (100) made of a second semiconductor material; the materials are different and have different CTEs; the method comprises the steps of: A) patterning the substrate (100) by an etching process so to form an array of pillars (110), the pillars (110) being laterally spaced from each other and having a top section (112) larger than a bottom section (114) and/or intermediate sections (116), B) depositing the second semiconductor material on top of the pillars (110) at a growth temperature so to form an epitaxial layer (200) generated by vertical and lateral growth, and C) inducing breaking of the pillars (110) by cooling the substrate (100) and the epitaxial layer (200) below the growth temperature.

Nanostructure channels of a nanostructure transistor are etched during a nanosheet release process for removing sacrificial nanostructure layers between the nanostructure channels. The nanostructure channels are etched such that the thickness of the nanostructure channels at the edges of the nanostructure channels is less than the thickness of the nanostructure channels at the centers of the nanostructure channels. This results in the nanostructure channels having a sloped/tapered or curved cross-sectional profile between the centers and the edges of the nanostructure channels. The resultant cross-section profile provides larger openings between vertically adjacent nanostructure channels for depositing material of a gate structure of the nanostructure transistor between vertically adjacent nanostructure channels of the nanostructure transistor. The larger openings increase the gap-filling performance for forming the gate structure, which reduces the likelihood of (and/or size of) seams and/or voids in the gate structure between vertically adjacent nanostructure channels.

In an example, a method of manufacturing a semiconductor device includes providing a semiconductor substrate comprising an unpolished CZ silicon substrate, a substrate upper side, and a substrate lower side opposite to the substrate upper side. The method includes first annealing the semiconductor substrate at a first temperature in an inert environment for a first time. The method includes second annealing the semiconductor substrate at a second temperature in a wet oxidation environment for a second time. The first annealing dissolves inner wall oxide in bulk region voids and the second annealing fills the voids with semiconductor interstitials. In some examples, the CZ silicon substrate is provided from a CZ ingot grown in the presence of a magnetic field and using continuous counter-doping. The method provides, among other things, a CZ silicon substrate with reduced crystal originated particle (COP) defects, reduced oxygen concentration, and reduced radial resistivity variation.

An etching method includes: (a) providing a substrate including an etching target film and a mask on the etching target film; (b) after (a), forming a metal-containing deposit on the mask by a first plasma generated from a first processing gas including a metal-containing gas and a hydrogen-containing gas; (c) after (b), deforming or modifying the metal-containing deposit by a second plasma generated from a second processing gas different from the first processing gas; and (d) after (c), etching the etching target film.

A substrate processing method includes preparing a substrate including a silicon layer, which is an example of an etching target that is at least one of silicon and polysilicon; and etching the etching target by supplying the substrate with hot AOM, which is an example of high-temperature ammonia water having a temperature higher than room temperature and an increased dissolved oxygen concentration.

Approaches herein provide devices and methods for forming optimized gate-all-around transistors. One method may include forming a plurality of nanosheets each comprising a plurality of alternating first layers and second layers, and etching the plurality of nanosheets to laterally recess the second layers relative to the first layers. The method may further include forming an inner spacer over the recessed second layers by forming a spacer material along an exposed portion of each of the plurality of nanosheets, etching the spacer material to remove the spacer material from the first layers of each of the plurality of nanosheets, and performing a sidewall treatment to the plurality of nanosheets after the spacer material is removed from the first layers of each of the plurality of nanosheets.

In order to have uniform dot holes even when a deep laser mark of approximately 100 m depth is formed, a silicon wafer having a crystal plane orientation of (100) has an identification mark configured by a plurality of dot holes on a surface with a surface roughness of 0.15 to 0.60 nm. A ratio between a length in a <100> direction and a length in a <110> direction of an opening of the dot hole on a wafer surface is 1 to 1.10, the length in the <100> direction of the opening is 80 m to 110 m, a depth of the dot hole in a cross-section is 80 m to 110 m, and a bottom surface of the dot hole is a flat surface of a (100) plane.

A manufacturing method of a semiconductor structure includes the following steps. A first wafer is provided. The first wafer includes a first substrate and a first device layer. A second wafer is provided. The second wafer includes a second substrate and a second device layer. The second device layer is bonded to the first device layer. An edge trimming process is performed on the first wafer and the second wafer to expose a first upper surface of the first substrate and a second upper surface of the first substrate and to form a damaged region in the first substrate below the first upper surface and the second upper surface. The second upper surface is higher than the first upper surface. A first photoresist layer is formed. The first photoresist layer is located on the second wafer and the second upper surface and exposes the first upper surface and the damaged region. The damaged region is removed by using the first photoresist layer as a mask. The first photoresist layer is removed.

Examples are disclosed that relate to planarizing substrates without use of an abrasive. One example provides a method of chemically planarizing a substrate, the method comprising introducing an abrasive-free planarization solution onto a porous pad, contacting the substrate with the porous pad while moving the porous pad and substrate relative to one another such that higher portions of the substrate contact the porous pad and lower portions of the substrate do not contact the porous pad, and removing material from the higher portions of the substrate via contact with the porous pad to reduce a height of the higher portions of the substrate relative to the lower portions of the substrate.