Patent classifications
H10P95/906
Nitride-containing STI liner for SIGE channel
A semiconductor device includes a fin structure that protrudes vertically out of a substrate, wherein the fin structure contains silicon germanium (SiGe). An epi-silicon layer is disposed on a sidewall of the fin structure. The epi-silicon layer contains nitrogen. One or more dielectric liner layers are disposed on the epi-silicon layer. A dielectric isolation structure is disposed over the one or more dielectric liner layers.
Fabrication of silicon germanium channel and silicon/silicon germanium dual channel field-effect transistors
A method for manufacturing a semiconductor device includes forming a plurality of fins on a substrate, wherein each fin of the plurality of fins includes silicon germanium. A layer of silicon germanium oxide is deposited on the plurality of fins, and a first thermal annealing process is performed to convert outer regions of the plurality of fins into a plurality of silicon portions. Each silicon portion of the plurality of silicon portions is formed on a silicon germanium core portion. The method further includes forming a plurality of source/drain regions on the substrate, and depositing a layer of germanium oxide on the plurality of source/drain regions. A second thermal annealing process is performed to convert outer regions of the plurality of source/drain regions into a plurality of germanium condensed portions.
NITRIDE-CONTAINING STI LINER FOR SIGE CHANNEL
A semiconductor device includes a fin structure that protrudes vertically out of a substrate, wherein the fin structure contains silicon germanium (SiGe). An epi-silicon layer is disposed on a sidewall of the fin structure. The epi-silicon layer contains nitrogen. One or more dielectric liner layers are disposed on the epi-silicon layer. A dielectric isolation structure is disposed over the one or more dielectric liner layers.