A method includes forming, over a substrate, a plurality of well taps arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of well taps is arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of well taps includes at least one first well tap. The forming the plurality of well taps comprises forming the first well tap by forming a first well region of a first type. The first well region comprises two first end areas and a first middle area arranged consecutively between the two first end areas in the second direction. The forming the first well tap further comprises implanting, in the first middle area, a first dopant of a first type, and implanting, in the first end areas, a second dopant of a second type different from the first type.

A method for forming a semiconductor structure includes following operations. First fins are formed in a first region of a substrate, and second fins are formed in a second region of the substrate. Widths of the first fins are greater than widths of the second fins. An isolation structure is formed over the substrate. A first ion implantation is performed on the first fins. A portion of the isolation structure is removed to expose a portion of each first fin and a portion of each second fin. The widths of the first fins are equal to or less than the widths of the second fins after the removing of the portion of the isolation structure. A 3D capacitor is formed in the first region, and a FinFET device is formed in the second region. The 3D capacitor includes the first fins, and the FinFET device includes the second fins.

A method for producing a semiconductor body comprises providing a first semiconductor layer of SiC, introducing carbon into the first semiconductor layer so that at least a portion of the first semiconductor layer becomes at least one C-rich region, and growing a second semiconductor layer of SiC on the first semiconductor layer comprising the at least one C-rich region.

A VDMOS device and a fabrication method thereof are provided. The device includes unit cells which jointly form a cellular structure. The cellular structure includes spaced-apart source regions and surrounding gate regions. Some gate regions overlap to form gate intersections comprising separation regions; the others form non-intersecting gate regions. Each unit cell has a JFET region corresponding in position to one non-intersecting gate region and a JFET shielding region corresponding in position to one gate intersection. The difference in doping concentrations of different types of dopants in the JFET shielding region surpasses difference in doping concentrations in the JFET regions and therefore depletion layers disposed along diagonals of the gate intersections expand and merge more easily, thereby increasing breakdown voltage along the diagonals. Therefore, the device exhibits enhanced voltage tolerance and stability.

The present disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes: a substrate doped with a first ion, a deep trench structure disposed in the substrate, a barrier doped region disposed on a top of the substrate and the deep trench structure, a first epitaxial layer disposed on the barrier doped region, a body region disposed in the first epitaxial layer, a source region disposed in the body region, a gate structure disposed in the first epitaxial layer, and a collector region disposed at a bottom of the substrate. By means of the semiconductor structure, performance of an insulated gate bipolar transistor can be improved.

A semiconductor device includes a gate structure, a drift region, a source region, a drain region, a first doped region, and a second doped region. The gate structure is over a semiconductor substrate. The drift region is in the semiconductor substrate and laterally extends past a first side of the gate structure. The source region is in the semiconductor substrate and adjacent a second side of the gate structure opposite the first side. The drain region is in the drift region. The first doped region is in the drift region and between the drain region and the gate structure. The second doped region is within the drift region. The second doped region forms a P-N junction with the first doped region at a bottom surface of the first doped region.

The present application discloses a method for manufacturing a metal zero layer, comprising: step 1, etching a zero interlayer film to form a first trench; step 2, performing first Ge ion implantation to form a first Ge layer in the zero interlayer film and achieve first amorphization; step 3, performing second Ge ion implantation to form a second Ge layer in the zero interlayer film and achieve second amorphization, wherein the depth of the second Ge layer is greater than the depth of the first Ge layer, and the second Ge ion implantation is tilt ion implantation; step 4, forming a metal silicide layer on the surface of an amorphous silicon layer in a self-aligned manner; step 5, filling the first trench with a first metal layer; and step 6, performing chemical mechanical polishing to fully remove the first metal layer outside the first trench and achieve planarization.

An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.

A gate electrode is formed inside a trench via a gate insulating film. The gate insulating film formed on a semiconductor substrate is removed. An insulating film is formed on the semiconductor substrate. A p-type base region is formed in the semiconductor substrate. An n-type emitter region is formed in the base region. Hydrogen annealing process is performed to the semiconductor substrate. A boundary between the base region and the emitter region is located at a position deeper than the insulating film formed between a side surface of the trench and the gate insulating film.

Disclosed is a trench-type power device and a manufacturing method thereof. The trench-type power device comprises: a semiconductor substrate; a drift region located on the semiconductor substrate; a first trench and a second trench located in the drift region; a gate stack located in the first trench; and Schottky metal located on a side wall of the second trench, wherein the Schottky metal and the drift region form a Schottky barrier diode. The trench-type power device adopts a double-trench structure, which combines a trench-type MOSFET with the Schottky barrier diode and forms the Schottky metal on the side wall of the trench, so that the performance of the power device can be improved, and the unit area of the power device can be reduced.