An integrated circuit is fabricated by forming transistors having gates of orthogonal orientations and implanting, at two first rotations, a first pocket implant using a first dopant type with a masking pattern on a substrate surface layer, the two first rotations respectively forming two first pocket implantation angles and two first pocket implantation beam orientations, and implanting, at two second rotations, a retrograde gate-edge diode leakage (GDL) reduction pocket implant using a second dopant type with the masking pattern on the substrate surface layer, the two second rotations respectively forming two GDL-reduction implantation angles and two GDL-reduction implantation beam orientations. Owing to the different symmetries in implantation angles seen by the two orientations of transistors, leakage is reduced for transistors of both orientations and mismatch is maintained for transistors of one of the orientations, making these transistors suitable for use in analog circuits requiring matched pairs of transistors.

An implantation device is disclosed. In particular, an implantation device includes an ionization chamber having a cathode and a repeller arranged therein. A source of aluminum ions is including within the chamber, wherein a displacing gas is introduced to the chamber during an ionization process to yield a beam of energetic aluminum ions.

Aspects include a transistor having a gate region with a uniform gate length and a body contact region abutted to a conduction channel under the gate region to improve mitigation of the kink effect, and related methods. The transistor includes the conduction channel formed from a semiconductor layer. A source region and a drain region of the transistor are formed on opposite sides of the conduction channel in the semiconductor layer. A gate region is formed adjacent to the conduction channel. The gate region has a gate length and a gate width. The transistor has a body contact region having a second polarity and directly adjacent to the second side of the conduction channel creating a body interface between the body contact region and the conduction channel. The gate length is uniform throughout the entire gate width including where the body contact region is directly adjacent to the conduction channel.

The present disclosure relates to an electronic device comprising a semiconductor substrate and transistors having their gates contained in trenches extending in the semiconductor substrate, each transistor comprising a doped semiconductor well of a first conductivity type, the well being buried in the semiconductor substrate and in contact with two adjacent trenches among said trenches, a first doped semiconductor region of a second conductivity type, covering the well, in contact with the well, and in contact with the two adjacent trenches, a second doped semiconductor region of the second conductivity type more heavily doped than the first semiconductor region, extending in the first semiconductor region, and a third doped semiconductor region of the first conductivity type, more heavily doped than the well, covering the well, in contact with the first region, and extending in the semiconductor substrate in contact with the well.

A manufacturing method of a semiconductor device includes following steps. A semiconductor substrate including a first portion in a low voltage device region and a second portion in a middle voltage device region is provided. A first gate structure and a second gate structure are formed above the first portion and the second portion, respectively. An implantation process is performed for forming a first source/drain doped region in the first portion and a second source/drain doped region in the second portion concurrently. A first oxide layer and a second oxide layer are located above the first portion and the second portion during the implantation process, respectively. The first source/drain doped region is formed under the first oxide layer. The second source/drain doped region is formed under the second oxide layer. A thickness of the second oxide layer is greater than or substantially equal to that of the first oxide layer.

An integrated circuit (IC) device includes a plurality of first taps arranged in a plurality of first columns and a plurality of first rows, and a plurality of second taps arranged in a plurality of second columns and a plurality of second rows. The plurality of second taps has a type different from the plurality of first taps. Each first tap of the plurality of first taps extends continuously across multiple rows of first active regions. Each second tap of the plurality of second taps extends continuously across multiple rows of second active regions. The second active regions have a type different from the first active regions. Along a column direction of the plurality of first columns and the plurality of second columns, no first tap among the plurality of first taps overlaps any second tap among the plurality of second taps.

A semiconductor device includes a gate structure, a drift region, a source region, a drain region, a first doped region, and a second doped region. The gate structure is over a semiconductor substrate. The drift region is in the semiconductor substrate and laterally extends past a first side of the gate structure. The source region is in the semiconductor substrate and adjacent a second side of the gate structure opposite the first side. The drain region is in the drift region. The first doped region is in the drift region and between the drain region and the gate structure. The second doped region is within the drift region. The second doped region forms a P-N junction with the first doped region at a bottom surface of the first doped region.

The present disclosure provides a semiconductor device, a method for manufacturing the semiconductor device, and electronic equipment including the semiconductor device. According to embodiments, a semiconductor device may include a channel portion, source/drain portions in contact with the channel portion on opposite sides of the channel portion, and a gate stack intersecting the channel portion. The channel portion includes a first part extending in a vertical direction relative to the substrate and a second part extending from the first part in a lateral direction relative to the substrate.

According to some embodiments of the present disclosure, methods of forming a semiconductor device on a semiconductor layer having opposing first and second surfaces are disclosed. An n-type doped region including an n-type dopant may be formed at the first surface of the semiconductor layer. A p-type dopant source layer including a p-type dopant may be formed on the n-type doped region. The p-type dopant may be diffused from the p-type dopant source layer through the n-type doped region into the semiconductor layer to form a p-type doped region of the semiconductor layer, and the p-type doped region of the semiconductor layer may be between the n-type doped region and the second surface of the semiconductor layer. After diffusing the p-type dopant, the p-type dopant source layer may be removed.

A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type. The semiconductor structure further includes a drift layer of the first conductivity type located above the semiconductor substrate, a channel layer of a second conductivity type located above the drift layer, and a source region of the first conductivity type located above the channel layer. The second conductivity type is opposite to the first conductivity type. A plurality of trenches penetrates through the source region, the channel layer and a portion of the drift region. A gate electrode is located within each of the plurality of trenches via a gate insulating film and a plurality of shielding structures of the second conductivity type is located around the gate electrode. The plurality of shielding structures covers sidewalls and a bottom of the plurality of trenches. The plurality of shielding structures is arranged in an island-like manner.