A semiconductor device includes an insulating layer (IFL) on a semiconductor substrate (SUB), a conductive film (PL) on the insulating layer (IFL), an interlayer insulating film (IL) covering the conductive film (PL), a contact hole (CH1) in the interlayer insulating film (IL), the conductive film (PL) and the insulating layer (IFL), and a plug (PG1) embedded in the contact hole (CH1). A side surface of the interlayer insulating film (IL) is separated from a side surface of the conductive film (PL) to expose a part of an upper surface of the conductive film (PL), and a side surface of the insulating layer (IFL) is separated from the side surface of the conductive film (PL) to expose a part of a lower surface of the conductive film (PL). A distance (L1) from the lower surface of the conductive film (PL) to the bottom of the contact hole (CH1) is longer than a distance (L2) from the side surface of the conductive film (PL) to the side surface of the interlayer insulating film (IL).

Described herein is a method of using a composition for selectively etching a silicon layer in the presence of a layer including a silicon germanium alloy, the composition including: (a) 4 to 15% by weight of an amine of formula (E1), and (b) water, where X.sup.E1, X.sup.E2, and X.sup.E3 are independently selected from a chemical bond and C.sub.1-C.sub.6 alkanediyl; Y.sup.E is selected from N, CR.sup.E1, and P; R.sup.E1 is selected from H and C.sub.1-C.sub.6 alkyl.

Provided is an etching method. The etching method includes loading a substrate into a process chamber, wherein the process chamber includes a first chamber part and a second chamber part, and the substrate is loaded into the second chamber part, supplying high-density gas plasma to the first chamber part, supplying ultra-low electron temperature plasma to the second chamber part using at least a portion of the high-density gas plasma, adsorbing radicals of the ultra-low electron temperature plasma to a surface of the substrate, and applying a bias to the substrate to accelerate at least one of ions or electrons of the ultra-low electron temperature plasma so as to collide with the substrate.

A method for forming a semiconductor structure and a method for forming a laminate structure include the following operations. A laminate structure is provided, the laminate structure including a plurality of sacrificial layers and a plurality of support layers alternately stacked on one another, each support layers includes a plurality of doped areas and a plurality of body areas. A first etching process is performed to form a plurality of first gaps penetrating through the plurality of body areas and the plurality of sacrificial layers in the laminate structure. A first material layer is deposited on inner walls of the plurality of first gaps. A second etching process is performed to remove the plurality of doped areas and the plurality of sacrificial layers to form a second gap between any two adjacent first gaps.

A method for etching a dielectric layer covering a top and a flank of a three-dimensional structure, this method including a first etching of the dielectric layer, including a first fluorine based compound, a second compound taken from SiwCl(2w+2) and SiwF(2w+2), oxygen, this first etching being carried out to form a first protective layer on the top and form a second protective layer on the dielectric layer, a second etching configured to remove the second protective layer while retaining a portion of the first protective layer, the first and second etchings being repeated until removing the dielectric layer located on the flank of the structure. The second etching can be carried out by hydrogen-based plasma.

A metal removal method which includes: a reaction step of bringing a treatment gas containing a fluorine-containing interhalogen compound and a metal-containing material containing a metal element into contact with each other to generate metal fluoride which is a reaction product of the fluorine-containing interhalogen compound and the metal element; and a volatilization step of heating the metal fluoride under an inert gas atmosphere or in a vacuum environment for volatilization. The metal element is at least one kind selected from iron, cobalt, nickel, selenium, molybdenum, rhodium, palladium, tungsten, rhenium, iridium, and platinum. Also disclosed is a dry etching method using the metal removal method and a production method for a semiconductor element using the dry etching method.

A method of manufacturing a semiconductor device may include sequentially forming a word line filling a word line trench of a substrate and a buried insulation layer on the word line, performing a first etching process of forming a logic active region contact hole extending to an inner portion of a logic active region of the substrate and a word line contact hole extending to an inner portion of the buried insulation layer, and performing a second etching process so that the word line contact hole extends to an inner portion of the word line. The first etching process may be performed using a first etching gas, which may include difluoromethane (CH.sub.2F.sub.2) and octafluorobutyne (C.sub.4F.sub.8) and where a ratio of difluoromethane to octafluorobutyne may be at least 1:1.5. The first etching gas may react with the logic active region to form a barrier layer.

A trench MOSFET includes a substrate, a gate structure, source regions, oxide spacers, a nitride cladding layer, an inner dielectric layer, a source contact, and a gate contact. The gate structure is disposed in a trench of the substrate and has a protruding top exposed from a surface of the substrate and having exposed sidewalls. The source regions are formed in the surface of the substrate on both sides of the gate structure. The oxide spacers are disposed on the exposed sidewalls of the protruding top. The nitride cladding layer conformally covers the oxide spacer and the surface of the substrate. The inner dielectric layer is deposited on the nitride cladding layer. The source contact window passes through the inner dielectric layer and the nitride cladding layer. The gate contact passes through the inner dielectric layer and the nitride cladding layer.

The present disclosure discloses a method for manufacturing a via, including: forming a first dielectric layer on the surface of an underlying structure; performing patterned etching on the first dielectric layer to form a via opening; forming a first metal layer; performing first-time metal CMP to remove the first metal layer on the outer surface of the via opening, where a top surface of the first metal layer in the via opening is located below a top surface of the first dielectric layer; performing second-time dielectric etch back, to selectively etch the first dielectric layer, lower the top surface of the first dielectric layer as being below the top surface of the first metal layer, and form a metal protrusion of a via; and forming a pattern of an upper metal interconnection layer.

A method of processing a substrate that includes: loading the substrate having a raised feature with at least two sidewalls exposed in a processing chamber; depositing a first layer over the substrate to cover a first portion of the two sidewalls; depositing a second layer over the first layer to cover a second portion of the two sidewalls; depositing a third layer over the second layer and the raised feature to cover a third portion of the sidewalls and a top surface of the raised feature; performing an anisotropic dry etching that removes portions of the second layer and the third layer, a remainder of the second layer forming a second sidewall spacer and a remainder of the third layer forming a third sidewall spacer; and performing an isotropic etching that selectively removes the second sidewall spacer to expose portions of the sidewalls of the raised feature.